90 lines
3.9 KiB
Verilog
90 lines
3.9 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// can_crc.v ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002, 2003, 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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// `include "timescale.v"
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// synopsys translate_on
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module can_crc (clk, data, enable, initialize, crc);
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parameter Tp = 1;
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input clk;
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input data;
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input enable;
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input initialize;
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output [14:0] crc;
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reg [14:0] crc;
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wire crc_next;
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wire [14:0] crc_tmp;
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assign crc_next = data ^ crc[14];
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assign crc_tmp = {crc[13:0], 1'b0};
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always @ (posedge clk)
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begin
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if(initialize)
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crc <= #Tp 15'h0;
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else if (enable)
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begin
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if (crc_next)
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crc <= #Tp crc_tmp ^ 15'h4599;
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else
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crc <= #Tp crc_tmp;
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end
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end
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endmodule
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