36 lines
769 B
VHDL
36 lines
769 B
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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--Generic BRAM with 64 Byte
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity blockram is
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port (
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clk : in std_logic;
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we : in std_logic;
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en : in std_logic;
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addr : in std_logic_vector(5 downto 0);
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di : in std_logic_vector(7 downto 0);
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do : out std_logic_vector(7 downto 0));
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end blockram;
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architecture syn of blockram is
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type ram_type is array (63 downto 0) of std_logic_vector (7 downto 0);
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signal RAM: ram_type;
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begin
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process (clk)
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begin
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if clk'event and clk = '1' then
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if en = '1' then
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if we = '1' then
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RAM(conv_integer(addr)) <= di;
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end if;
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do <= RAM(conv_integer(addr)) ;
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end if;
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end if;
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end process;
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end syn;
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