716 lines
19 KiB
Verilog
716 lines
19 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// can_top.v ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002, 2003, 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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//`include "timescale.v" //commented this out, see what breaks... -TF
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// synopsys translate_on
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`include "can_defines.v"
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module can_top
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(
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`ifdef CAN_WISHBONE_IF
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wb_clk_i,
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wb_rst_i,
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wb_dat_i,
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wb_dat_o,
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wb_cyc_i,
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wb_stb_i,
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wb_we_i,
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wb_adr_i,
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wb_ack_o,
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`else
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rst_i,
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ale_i,
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rd_i,
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wr_i,
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port_0_io,
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cs_can_i,
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`endif
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clk_i,
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rx_i,
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tx_o,
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bus_off_on,
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irq_on,
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clkout_o
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// Bist
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`ifdef CAN_BIST
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,
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// debug chain signals
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mbist_si_i, // bist scan serial in
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mbist_so_o, // bist scan serial out
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mbist_ctrl_i // bist chain shift control
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`endif
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);
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parameter Tp = 1;
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`ifdef CAN_WISHBONE_IF
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input wb_clk_i;
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input wb_rst_i;
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input [7:0] wb_dat_i;
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output [7:0] wb_dat_o;
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input wb_cyc_i;
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input wb_stb_i;
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input wb_we_i;
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input [7:0] wb_adr_i;
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output wb_ack_o;
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reg wb_ack_o;
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reg cs_sync1;
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reg cs_sync2;
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reg cs_sync3;
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reg cs_ack1;
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reg cs_ack2;
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reg cs_ack3;
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reg cs_sync_rst1;
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reg cs_sync_rst2;
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wire cs_can_i;
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`else
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input rst_i;
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input ale_i;
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input rd_i;
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input wr_i;
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inout [7:0] port_0_io;
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input cs_can_i;
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reg [7:0] addr_latched;
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reg wr_i_q;
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reg rd_i_q;
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`endif
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input clk_i;
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input rx_i;
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output tx_o;
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output bus_off_on;
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output irq_on;
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output clkout_o;
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// Bist
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`ifdef CAN_BIST
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input mbist_si_i; // bist scan serial in
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output mbist_so_o; // bist scan serial out
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input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
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`endif
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reg data_out_fifo_selected;
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wire [7:0] data_out_fifo;
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wire [7:0] data_out_regs;
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/* Mode register */
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wire reset_mode;
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wire listen_only_mode;
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wire acceptance_filter_mode;
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wire self_test_mode;
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/* Command register */
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wire release_buffer;
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wire tx_request;
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wire abort_tx;
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wire self_rx_request;
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wire single_shot_transmission;
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wire tx_state;
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wire tx_state_q;
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wire overload_request;
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wire overload_frame;
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/* Arbitration Lost Capture Register */
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wire read_arbitration_lost_capture_reg;
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/* Error Code Capture Register */
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wire read_error_code_capture_reg;
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wire [7:0] error_capture_code;
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/* Bus Timing 0 register */
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wire [5:0] baud_r_presc;
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wire [1:0] sync_jump_width;
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/* Bus Timing 1 register */
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wire [3:0] time_segment1;
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wire [2:0] time_segment2;
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wire triple_sampling;
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/* Error Warning Limit register */
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wire [7:0] error_warning_limit;
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/* Rx Error Counter register */
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wire we_rx_err_cnt;
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/* Tx Error Counter register */
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wire we_tx_err_cnt;
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/* Clock Divider register */
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wire extended_mode;
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/* This section is for BASIC and EXTENDED mode */
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/* Acceptance code register */
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wire [7:0] acceptance_code_0;
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/* Acceptance mask register */
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wire [7:0] acceptance_mask_0;
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/* End: This section is for BASIC and EXTENDED mode */
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/* This section is for EXTENDED mode */
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/* Acceptance code register */
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wire [7:0] acceptance_code_1;
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wire [7:0] acceptance_code_2;
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wire [7:0] acceptance_code_3;
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/* Acceptance mask register */
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wire [7:0] acceptance_mask_1;
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wire [7:0] acceptance_mask_2;
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wire [7:0] acceptance_mask_3;
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/* End: This section is for EXTENDED mode */
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/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
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wire [7:0] tx_data_0;
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wire [7:0] tx_data_1;
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wire [7:0] tx_data_2;
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wire [7:0] tx_data_3;
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wire [7:0] tx_data_4;
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wire [7:0] tx_data_5;
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wire [7:0] tx_data_6;
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wire [7:0] tx_data_7;
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wire [7:0] tx_data_8;
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wire [7:0] tx_data_9;
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wire [7:0] tx_data_10;
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wire [7:0] tx_data_11;
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wire [7:0] tx_data_12;
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/* End: Tx data registers */
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wire cs;
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/* Output signals from can_btl module */
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wire sample_point;
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wire sampled_bit;
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wire sampled_bit_q;
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wire tx_point;
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wire hard_sync;
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/* output from can_bsp module */
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wire rx_idle;
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wire transmitting;
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wire transmitter;
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wire go_rx_inter;
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wire not_first_bit_of_inter;
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wire set_reset_mode;
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wire node_bus_off;
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wire error_status;
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wire [7:0] rx_err_cnt;
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wire [7:0] tx_err_cnt;
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wire rx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
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wire tx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
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wire transmit_status;
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wire receive_status;
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wire tx_successful;
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wire need_to_tx;
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wire overrun;
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wire info_empty;
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wire set_bus_error_irq;
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wire set_arbitration_lost_irq;
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wire [4:0] arbitration_lost_capture;
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wire node_error_passive;
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wire node_error_active;
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wire [6:0] rx_message_counter;
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wire tx_next;
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wire go_overload_frame;
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wire go_error_frame;
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wire go_tx;
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wire send_ack;
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wire rst;
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wire we;
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wire [7:0] addr;
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wire [7:0] data_in;
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reg [7:0] data_out;
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reg rx_sync_tmp;
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reg rx_sync;
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/* Connecting can_registers module */
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can_registers i_can_registers
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(
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.clk(clk_i),
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.rst(rst),
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.cs(cs),
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.we(we),
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.addr(addr),
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.data_in(data_in),
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.data_out(data_out_regs),
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.irq_n(irq_on),
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.sample_point(sample_point),
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.transmitting(transmitting),
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.set_reset_mode(set_reset_mode),
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.node_bus_off(node_bus_off),
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.error_status(error_status),
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.rx_err_cnt(rx_err_cnt),
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.tx_err_cnt(tx_err_cnt),
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.transmit_status(transmit_status),
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.receive_status(receive_status),
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.tx_successful(tx_successful),
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.need_to_tx(need_to_tx),
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.overrun(overrun),
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.info_empty(info_empty),
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.set_bus_error_irq(set_bus_error_irq),
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.set_arbitration_lost_irq(set_arbitration_lost_irq),
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.arbitration_lost_capture(arbitration_lost_capture),
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.node_error_passive(node_error_passive),
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.node_error_active(node_error_active),
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.rx_message_counter(rx_message_counter),
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/* Mode register */
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.reset_mode(reset_mode),
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.listen_only_mode(listen_only_mode),
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.acceptance_filter_mode(acceptance_filter_mode),
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.self_test_mode(self_test_mode),
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/* Command register */
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.clear_data_overrun(),
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.release_buffer(release_buffer),
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.abort_tx(abort_tx),
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.tx_request(tx_request),
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.self_rx_request(self_rx_request),
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.single_shot_transmission(single_shot_transmission),
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.tx_state(tx_state),
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.tx_state_q(tx_state_q),
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.overload_request(overload_request),
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.overload_frame(overload_frame),
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/* Arbitration Lost Capture Register */
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.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
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/* Error Code Capture Register */
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.read_error_code_capture_reg(read_error_code_capture_reg),
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.error_capture_code(error_capture_code),
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/* Bus Timing 0 register */
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.baud_r_presc(baud_r_presc),
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.sync_jump_width(sync_jump_width),
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/* Bus Timing 1 register */
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.time_segment1(time_segment1),
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.time_segment2(time_segment2),
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.triple_sampling(triple_sampling),
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/* Error Warning Limit register */
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.error_warning_limit(error_warning_limit),
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/* Rx Error Counter register */
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.we_rx_err_cnt(we_rx_err_cnt),
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/* Tx Error Counter register */
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.we_tx_err_cnt(we_tx_err_cnt),
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/* Clock Divider register */
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.extended_mode(extended_mode),
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.clkout(clkout_o),
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/* This section is for BASIC and EXTENDED mode */
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/* Acceptance code register */
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.acceptance_code_0(acceptance_code_0),
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/* Acceptance mask register */
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.acceptance_mask_0(acceptance_mask_0),
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/* End: This section is for BASIC and EXTENDED mode */
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/* This section is for EXTENDED mode */
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/* Acceptance code register */
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.acceptance_code_1(acceptance_code_1),
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.acceptance_code_2(acceptance_code_2),
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.acceptance_code_3(acceptance_code_3),
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/* Acceptance mask register */
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.acceptance_mask_1(acceptance_mask_1),
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.acceptance_mask_2(acceptance_mask_2),
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.acceptance_mask_3(acceptance_mask_3),
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/* End: This section is for EXTENDED mode */
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/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
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.tx_data_0(tx_data_0),
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.tx_data_1(tx_data_1),
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.tx_data_2(tx_data_2),
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.tx_data_3(tx_data_3),
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.tx_data_4(tx_data_4),
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.tx_data_5(tx_data_5),
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.tx_data_6(tx_data_6),
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.tx_data_7(tx_data_7),
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.tx_data_8(tx_data_8),
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.tx_data_9(tx_data_9),
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.tx_data_10(tx_data_10),
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.tx_data_11(tx_data_11),
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.tx_data_12(tx_data_12)
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/* End: Tx data registers */
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);
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/* Connecting can_btl module */
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can_btl i_can_btl
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(
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.clk(clk_i),
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.rst(rst),
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.rx(rx_sync),
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.tx(tx_o),
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/* Bus Timing 0 register */
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.baud_r_presc(baud_r_presc),
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.sync_jump_width(sync_jump_width),
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/* Bus Timing 1 register */
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.time_segment1(time_segment1),
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.time_segment2(time_segment2),
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.triple_sampling(triple_sampling),
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/* Output signals from this module */
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.sample_point(sample_point),
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.sampled_bit(sampled_bit),
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.sampled_bit_q(sampled_bit_q),
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.tx_point(tx_point),
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.hard_sync(hard_sync),
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/* output from can_bsp module */
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.rx_idle(rx_idle),
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.rx_inter(rx_inter),
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.transmitting(transmitting),
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.transmitter(transmitter),
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.go_rx_inter(go_rx_inter),
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.tx_next(tx_next),
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.go_overload_frame(go_overload_frame),
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.go_error_frame(go_error_frame),
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.go_tx(go_tx),
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.send_ack(send_ack),
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.node_error_passive(node_error_passive)
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);
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can_bsp i_can_bsp
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(
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.clk(clk_i),
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.rst(rst),
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/* From btl module */
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.sample_point(sample_point),
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.sampled_bit(sampled_bit),
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.sampled_bit_q(sampled_bit_q),
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.tx_point(tx_point),
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.hard_sync(hard_sync),
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.addr(addr),
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.data_in(data_in),
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.data_out(data_out_fifo),
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.fifo_selected(data_out_fifo_selected),
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/* Mode register */
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.reset_mode(reset_mode),
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.listen_only_mode(listen_only_mode),
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.acceptance_filter_mode(acceptance_filter_mode),
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.self_test_mode(self_test_mode),
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/* Command register */
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.release_buffer(release_buffer),
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.tx_request(tx_request),
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.abort_tx(abort_tx),
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.self_rx_request(self_rx_request),
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.single_shot_transmission(single_shot_transmission),
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.tx_state(tx_state),
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.tx_state_q(tx_state_q),
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.overload_request(overload_request),
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.overload_frame(overload_frame),
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/* Arbitration Lost Capture Register */
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.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
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/* Error Code Capture Register */
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.read_error_code_capture_reg(read_error_code_capture_reg),
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.error_capture_code(error_capture_code),
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/* Error Warning Limit register */
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.error_warning_limit(error_warning_limit),
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/* Rx Error Counter register */
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.we_rx_err_cnt(we_rx_err_cnt),
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/* Tx Error Counter register */
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.we_tx_err_cnt(we_tx_err_cnt),
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/* Clock Divider register */
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.extended_mode(extended_mode),
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/* output from can_bsp module */
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.rx_idle(rx_idle),
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.transmitting(transmitting),
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.transmitter(transmitter),
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.go_rx_inter(go_rx_inter),
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.not_first_bit_of_inter(not_first_bit_of_inter),
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.rx_inter(rx_inter),
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.set_reset_mode(set_reset_mode),
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.node_bus_off(node_bus_off),
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.error_status(error_status),
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.rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
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.tx_err_cnt({tx_err_cnt_dummy, tx_err_cnt[7:0]}), // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
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.transmit_status(transmit_status),
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.receive_status(receive_status),
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.tx_successful(tx_successful),
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.need_to_tx(need_to_tx),
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.overrun(overrun),
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.info_empty(info_empty),
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.set_bus_error_irq(set_bus_error_irq),
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.set_arbitration_lost_irq(set_arbitration_lost_irq),
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.arbitration_lost_capture(arbitration_lost_capture),
|
|
.node_error_passive(node_error_passive),
|
|
.node_error_active(node_error_active),
|
|
.rx_message_counter(rx_message_counter),
|
|
|
|
/* This section is for BASIC and EXTENDED mode */
|
|
/* Acceptance code register */
|
|
.acceptance_code_0(acceptance_code_0),
|
|
|
|
/* Acceptance mask register */
|
|
.acceptance_mask_0(acceptance_mask_0),
|
|
/* End: This section is for BASIC and EXTENDED mode */
|
|
|
|
/* This section is for EXTENDED mode */
|
|
/* Acceptance code register */
|
|
.acceptance_code_1(acceptance_code_1),
|
|
.acceptance_code_2(acceptance_code_2),
|
|
.acceptance_code_3(acceptance_code_3),
|
|
|
|
/* Acceptance mask register */
|
|
.acceptance_mask_1(acceptance_mask_1),
|
|
.acceptance_mask_2(acceptance_mask_2),
|
|
.acceptance_mask_3(acceptance_mask_3),
|
|
/* End: This section is for EXTENDED mode */
|
|
|
|
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
|
|
.tx_data_0(tx_data_0),
|
|
.tx_data_1(tx_data_1),
|
|
.tx_data_2(tx_data_2),
|
|
.tx_data_3(tx_data_3),
|
|
.tx_data_4(tx_data_4),
|
|
.tx_data_5(tx_data_5),
|
|
.tx_data_6(tx_data_6),
|
|
.tx_data_7(tx_data_7),
|
|
.tx_data_8(tx_data_8),
|
|
.tx_data_9(tx_data_9),
|
|
.tx_data_10(tx_data_10),
|
|
.tx_data_11(tx_data_11),
|
|
.tx_data_12(tx_data_12),
|
|
/* End: Tx data registers */
|
|
|
|
/* Tx signal */
|
|
.tx(tx_o),
|
|
.tx_next(tx_next),
|
|
.bus_off_on(bus_off_on),
|
|
|
|
.go_overload_frame(go_overload_frame),
|
|
.go_error_frame(go_error_frame),
|
|
.go_tx(go_tx),
|
|
.send_ack(send_ack)
|
|
|
|
|
|
`ifdef CAN_BIST
|
|
,
|
|
/* BIST signals */
|
|
.mbist_si_i(mbist_si_i),
|
|
.mbist_so_o(mbist_so_o),
|
|
.mbist_ctrl_i(mbist_ctrl_i)
|
|
`endif
|
|
);
|
|
|
|
|
|
|
|
// Multiplexing wb_dat_o from registers and rx fifo
|
|
always @ (extended_mode or addr or reset_mode)
|
|
begin
|
|
if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
|
|
data_out_fifo_selected = 1'b1;
|
|
else
|
|
data_out_fifo_selected = 1'b0;
|
|
end
|
|
|
|
|
|
always @ (posedge clk_i)
|
|
begin
|
|
if (cs & (~we))
|
|
begin
|
|
if (data_out_fifo_selected)
|
|
data_out <=#Tp data_out_fifo;
|
|
else
|
|
data_out <=#Tp data_out_regs;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
always @ (posedge clk_i or posedge rst)
|
|
begin
|
|
if (rst)
|
|
begin
|
|
rx_sync_tmp <= 1'b1;
|
|
rx_sync <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
rx_sync_tmp <=#Tp rx_i;
|
|
rx_sync <=#Tp rx_sync_tmp;
|
|
end
|
|
end
|
|
|
|
|
|
|
|
`ifdef CAN_WISHBONE_IF
|
|
|
|
assign cs_can_i = 1'b1;
|
|
|
|
// Combining wb_cyc_i and wb_stb_i signals to cs signal. Than synchronizing to clk_i clock domain.
|
|
always @ (posedge clk_i or posedge rst)
|
|
begin
|
|
if (rst)
|
|
begin
|
|
cs_sync1 <= 1'b0;
|
|
cs_sync2 <= 1'b0;
|
|
cs_sync3 <= 1'b0;
|
|
cs_sync_rst1 <= 1'b0;
|
|
cs_sync_rst2 <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
cs_sync1 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
|
|
cs_sync2 <=#Tp cs_sync1 & (~cs_sync_rst2);
|
|
cs_sync3 <=#Tp cs_sync2 & (~cs_sync_rst2);
|
|
cs_sync_rst1 <=#Tp cs_ack3;
|
|
cs_sync_rst2 <=#Tp cs_sync_rst1;
|
|
end
|
|
end
|
|
|
|
|
|
assign cs = cs_sync2 & (~cs_sync3);
|
|
|
|
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
cs_ack1 <=#Tp cs_sync3;
|
|
cs_ack2 <=#Tp cs_ack1;
|
|
cs_ack3 <=#Tp cs_ack2;
|
|
end
|
|
|
|
|
|
|
|
// Generating acknowledge signal
|
|
always @ (posedge wb_clk_i)
|
|
begin
|
|
wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
|
|
end
|
|
|
|
|
|
assign rst = wb_rst_i;
|
|
assign we = wb_we_i;
|
|
assign addr = wb_adr_i;
|
|
assign data_in = wb_dat_i;
|
|
assign wb_dat_o = data_out;
|
|
|
|
|
|
`else
|
|
|
|
// Latching address
|
|
always @ (posedge clk_i or posedge rst)
|
|
begin
|
|
if (rst)
|
|
addr_latched <= 8'h0;
|
|
else if (ale_i)
|
|
addr_latched <=#Tp port_0_io;
|
|
end
|
|
|
|
|
|
// Generating delayed wr_i and rd_i signals
|
|
always @ (posedge clk_i or posedge rst)
|
|
begin
|
|
if (rst)
|
|
begin
|
|
wr_i_q <= 1'b0;
|
|
rd_i_q <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
wr_i_q <=#Tp wr_i;
|
|
rd_i_q <=#Tp rd_i;
|
|
end
|
|
end
|
|
|
|
|
|
assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;
|
|
|
|
|
|
assign rst = rst_i;
|
|
assign we = wr_i;
|
|
assign addr = addr_latched;
|
|
assign data_in = port_0_io;
|
|
assign port_0_io = (cs_can_i & rd_i)? data_out : 8'hz;
|
|
|
|
`endif
|
|
|
|
|
|
endmodule
|