183 lines
3.7 KiB
VHDL
183 lines
3.7 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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library std;
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use std.standard.all;
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use std.textio.all;
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library work;
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use work.wishbone.all;
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use work.config.all;
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use work.txt_util.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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ENTITY corewrap_tb IS
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END corewrap_tb;
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ARCHITECTURE behavior OF corewrap_tb IS
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component corewrapper
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generic(
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wbidx: integer := 0
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_imem : in imem_core;
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out_imem : out core_imem;
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in_proc : in irq_core;
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out_proc : out core_irq;
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hardfault : out std_logic;
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wmsti : in wb_mst_in_type;
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wmsto : out wb_mst_out_type
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);
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end component;
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component irq_controller
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_proc : in core_irq;
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out_proc : out irq_core;
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irq_lines : in std_logic_vector((2 ** irq_num_width) - 1 downto 0)
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);
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end component;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal in_imem : imem_core;
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signal in_proc : irq_core;
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signal wmsti : wb_mst_in_type := wbm_in_none;
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--Outputs
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signal out_imem : core_imem;
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signal out_proc : core_irq;
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signal hardfault : std_logic;
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signal wmsto : wb_mst_out_type;
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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--internal signal
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--signal irq2core : irq_core;
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--signal core2irq : core_irq;
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signal irq_lines : std_logic_vector((2 ** irq_num_width) - 1 downto 0) := (others => '0');
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: corewrapper
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generic map(
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wbidx => CFG_LT16
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)
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port map(
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clk => clk,
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rst => rst,
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in_imem => in_imem,
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out_imem => out_imem,
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in_proc => in_proc,
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out_proc => out_proc,
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hardfault => hardfault,
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wmsti => wmsti,
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wmsto => wmsto
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);
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irqcontr_inst: irq_controller
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port map(
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clk => clk,
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rst => rst,
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in_proc => out_proc,
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out_proc => in_proc,
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irq_lines => irq_lines
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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reset : process is
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begin
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rst <= '1';
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wait for 3.5 * clk_period;
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rst <= '0';
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wait;
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end process reset;
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irq_stimuli : process is
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begin
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irq_lines(irq_lines'high downto 3) <= (others => '0');
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irq_lines(0) <= '0';
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--irq_lines(1) <= hardfault;
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wait;
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end process irq_stimuli;
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-- Stimulus process
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stim_proc: process
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begin
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--init
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in_imem.read_data <= (others=>'0');
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in_imem.ready <= '0';
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wmsti <= wbm_in_none;
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--end init
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clk_period*10;
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--------------------------------------
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-- Test_case 00:
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--------------------------------------
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-- No request
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-- Expected output all control signal should be inactive
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-- Expected error: None
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--------------------------------------
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--report ">> TC0 starts <<";
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--------------------------------------
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--data
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assert wmsti.ack = '1'
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report"E-00: No data request, but msti.ack for dmem should always be active"
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severity error;
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--ins
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assert in_imem.ready = '1'
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report"E-01: No ins request, but in_imem.ready should always be active"
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severity error;
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--------------------------------------
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--report ">> TC0 ends <<";
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--------------------------------------
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--
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--E N D Test_case 00
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--
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--------------------------------------
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--/////////////////////////////////////////
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assert false
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report ">>>> Simulation beendet!"
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severity failure;
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end process;
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END;
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