572 lines
17 KiB
VHDL
572 lines
17 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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library std;
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use std.standard.all;
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use std.textio.all;
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library work;
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use work.wishbone.all;
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use work.config.all;
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use work.txt_util.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.lt16soc_memories.all;
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ENTITY memwrap_tb IS
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END memwrap_tb;
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ARCHITECTURE behavior OF memwrap_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal in_imem : core_imem;
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signal wslvi : wb_slv_in_type := wbs_in_none;
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--Outputs
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signal out_imem : imem_core;
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signal fault : std_logic;
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signal out_byte : std_logic_vector(7 downto 0);
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signal wslvo : wb_slv_out_type;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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memwrap_inst: memwrapper
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generic map(
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memaddr => CFG_BADR_MEM,
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addrmask => CFG_MADR_MEM,
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wbidx => CFG_MEM,
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filename => "sample-programs\dummy.ram",
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size => IMEMSZ
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)
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port map(
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clk => clk,
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rst => rst,
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in_imem => in_imem,
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out_imem => out_imem,
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fault => fault, --irq_lines(2),
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wslvi => wslvi,
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wslvo => wslvo
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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reset : process is
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begin
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rst <= '1';
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wait for 3.5 * clk_period;
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rst <= '0';
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wait;
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end process reset;
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-- Stimulus process
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stim_proc: process
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variable tmpadr : std_logic_vector(memory_width - 1 downto 0) := (others=>'0');
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begin
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--init
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in_imem.read_addr <= (others=>'0');
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in_imem.read_en <= '1'; -- always read
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wslvi <= wbs_in_none;
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--end init
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clk_period*10;
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--------------------------------------
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-- Test_case 00:
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--------------------------------------
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-- No request
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-- Expected output all control signal should be inactive
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-- Expected error: None
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--------------------------------------
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--report ">> TC0 starts <<";
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--------------------------------------
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assert wslvo.ack = '1'
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report"E-00: No request, but slvo.ack for dmem should always be active"
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severity error;
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assert out_imem.ready = '1'
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report"E-01: No request, but out_imem.ready should always be active"
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severity error;
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--------------------------------------
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--report ">> TC0 ends <<";
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--------------------------------------
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--
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--E N D Test_case 00
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--
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--------------------------------------
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--------------------------------------
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-- Test_case 01:
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--------------------------------------
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-- Single ins read
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-- Expected output ins is read correctly
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-- Expected error: None
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-- 32b_adr = x"00000052", 30b_adr = x"00000014"
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-- data at the adr = x49303230 (ascii, I020)
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--------------------------------------
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--report ">> TC1 starts <<";
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--------------------------------------
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--data
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assert wslvo.ack = '1'
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report"E-10: No request, but slvo.ack for dmem should always be active"
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severity error;
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--ins
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in_imem.read_en <= '1'; in_imem.read_addr <= x"00000052"; wait for clk_period;
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assert out_imem.read_data = x"49303230" and out_imem.ready = '1'--value in ascii = I020
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report "E-11: ins_RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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severity error;
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--
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--------------------------------------
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--report ">> TC1 ends <<";
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--------------------------------------
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--
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--E N D Test_case 01
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--
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--------------------------------------
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--init
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in_imem.read_addr <= (others=>'0');
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in_imem.read_en <= '1';
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wslvi <= wbs_in_none;
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wait for clk_period;
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--end init
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--------------------------------------
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-- Test_case 02:
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--------------------------------------
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-- Single data read
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-- Expected output ins is read correctly
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-- Expected error: None
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-- 32b_adr = x"00000210", 30b_adr = x"00000084"
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-- data at the adr = x44303034 (ascii, D004)
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--------------------------------------
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--report ">> TC2 starts <<";
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--------------------------------------
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--data
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-- Handshake-1 (in):
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tmpadr := x"00000210";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= (others=>'0');
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wslvi.we <= '0'; -- read
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wslvi.sel <= "1000"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x30
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-2 (out):
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assert wslvo.dat = x"44000000" and wslvo.ack = '1'
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report"E-20: wrong data, Return data: " & hstr(wslvo.dat) & " Expected data: " & hstr(x"44000000")
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severity error;
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--ins
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assert out_imem.ready = '1'
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report"E-21: No request, but out_imem should always be active"
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severity error;
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----------------
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--------------------------------------
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--report ">> TC2 ends <<";
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--------------------------------------
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--
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--E N D Test_case 02
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--
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--------------------------------------
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--init
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in_imem.read_addr <= (others=>'0');
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in_imem.read_en <= '1';
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wslvi <= wbs_in_none;
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wait for clk_period;
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--end init
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--------------------------------------
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-- Test_case 03:
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--------------------------------------
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-- Single data write, non overlap addr
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-- write in address range of data
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-- given data at addr[0000_00215] = x"44303035"; (ascii = D005)
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-- B0 = x49, B2 = x30, B1 = x30, B0 = x35
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-- Expected output Return ack, written data is converted correctly
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-- Expected error: None
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--------------------------------------
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--report ">> TC3 starts <<";
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--------------------------------------
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--data
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-- Handshake-1 (in):
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tmpadr := x"00000215";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= x"AA35AAAA"; -- feed full data but take written only B2 (feed junk for the rest portion, making sure only sel part is taken)
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wslvi.we <= '1'; -- write
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wslvi.sel <= "0100"; -- sel_byte = B1 -> expected writted data portion = x35
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-2 (out):
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assert wslvo.ack = '1'
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report"E-30: WR request, No ack "
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severity error;
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--Read value for checking written value
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-- Handshake-3 (in):
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--tmpadr := x"0000000B";
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--wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= (others=>'0');
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wslvi.we <= '0'; -- read
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wslvi.sel <= "0100"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x35
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-4 (out):
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assert wslvo.dat = x"00350000" and wslvo.ack = '1'
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report"E-31: wrong data, Return data: " & hstr(wslvo.dat) & " Expected data: " & hstr(x"00350000")
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severity error;
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--ins
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assert out_imem.ready = '1'
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report"E-32: No request, but out_imem should always be active"
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severity error;
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--------------------------------------
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--report ">> TC3 ends <<";
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--------------------------------------
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--
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--E N D Test_case 03
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--
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--------------------------------------
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--init
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in_imem.read_addr <= (others=>'0');
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in_imem.read_en <= '1';
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wslvi <= wbs_in_none;
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wait for clk_period;
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--end init
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--------------------------------------
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-- Test_case 04:
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--------------------------------------
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-- Single data write, overlap addr
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-- write in address range of data
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-- given data at addr[0000_00015] = x"49303035"; (ascii = I005)
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-- B0 = x49, B2 = x30, B1 = x30, B0 = x35
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-- Expected output Return ack, written data is converted correctly
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-- Expected error: None
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--------------------------------------
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--report ">> TC4 starts <<";
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--------------------------------------
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--data
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-- Handshake-1 (in):
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tmpadr := x"00000015";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= x"AA35AAAA"; -- feed full data but take written only B2 (feed junk for the rest portion, making sure only sel part is taken)
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wslvi.we <= '1'; -- write
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wslvi.sel <= "0100"; -- sel_byte = B1 -> expected writted data portion = x35
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-2 (out):
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assert wslvo.ack = '1'
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report"E-40: WR request, No ack "
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severity error;
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--Read value for checking written value
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-- Handshake-3 (in):
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--tmpadr := x"0000000B";
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--wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= (others=>'0');
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wslvi.we <= '0'; -- read
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wslvi.sel <= "0100"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x35
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-4 (out):
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assert wslvo.dat = x"00350000" and wslvo.ack = '1'
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report"E-41: wrong data, Return data: " & hstr(wslvo.dat) & " Expected data: " & hstr(x"00350000")
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severity error;
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--ins
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assert out_imem.ready = '0'
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report"E-42: Read data address is in ins address range, thus imem.ready should be hold to grant to the slv"
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severity error;
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--------------------------------------
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--report ">> TC4 ends <<";
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--------------------------------------
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--
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--E N D Test_case 04
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--
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--------------------------------------
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--init
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in_imem.read_addr <= (others=>'0');
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in_imem.read_en <= '1';
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wslvi <= wbs_in_none;
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wait for clk_period;
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--end init
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--------------------------------------
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-- Test_case 05:
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--------------------------------------
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-- Sim ins/data read, non overlap address
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-- Expected output ins/data is read correctly
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-- Expected error: None
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--
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-- >> data_info
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-- 32b_adr = x"00000210", 30b_adr = x"00000084"
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-- data at the adr = x44303034 (ascii, D004)
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--
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-- >> ins_info
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-- 32b_adr = x"00000052", 30b_adr = x"00000014"
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-- data at the adr = x49303230 (ascii, I020)
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--------------------------------------
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--------------------------------------
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--report ">> TC5 starts <<";
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--------------------------------------
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-- Handshake-1 (in):
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-- data
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tmpadr := x"00000210";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= (others=>'0');
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wslvi.we <= '0'; -- read
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wslvi.sel <= "1000"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x30
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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-- ins
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in_imem.read_en <= '1'; in_imem.read_addr <= x"00000052";
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wait for clk_period;
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-- Handshake-2 (out):
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-- data
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assert wslvo.dat = x"44000000" and wslvo.ack = '1'
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report"E-50: wrong data, Return data: " & hstr(wslvo.dat) & " Expected data: " & hstr(x"44000000")
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severity error;
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-- ins
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assert out_imem.read_data = x"49303230" and out_imem.ready = '1'--value in ascii = I020
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report "E-51: ins_RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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severity error;
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--------------------------------------
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--report ">> TC5 ends <<";
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--------------------------------------
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--
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--E N D Test_case 05
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--
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--------------------------------------
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--init
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in_imem.read_addr <= (others=>'0');
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in_imem.read_en <= '1';
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wslvi <= wbs_in_none;
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wait for clk_period;
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--end init
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--------------------------------------
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-- Test_case 06:
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--------------------------------------
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-- Sim ins/data read, overlap address range
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-- Expected output ins/data is read correctly
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-- Expected error: None
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--
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-- >> data_info
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-- 32b_adr = x"00000056", 30b_adr = x"00000015"
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-- data at the adr = x49303231 (ascii, I021)
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--
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-- >> ins_info
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-- 32b_adr = x"00000052", 30b_adr = x"00000014"
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-- data at the adr = x49303230 (ascii, I020)
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--------------------------------------
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--------------------------------------
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--report ">> TC6 starts <<";
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--------------------------------------
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-- Handshake-1 (in):
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-- data
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tmpadr := x"00000056";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= (others=>'0');
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wslvi.we <= '0'; -- read
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wslvi.sel <= "0010"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x30
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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-- ins
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in_imem.read_en <= '1'; in_imem.read_addr <= x"00000052";
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wait for clk_period;
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-- Handshake-2 (out):
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-- data
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assert wslvo.dat = x"00003200" and wslvo.ack = '1'
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report"E-60: wrong data, Return data: " & hstr(wslvo.dat) & " Expected data: " & hstr(x"00003200")
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severity error;
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-- ins
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assert out_imem.read_data = x"49303230" and out_imem.ready = '0' -- overlap address range, ready must be inactive
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report "E-61: ins_RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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severity error;
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--------------------------------------
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--report ">> TC6 ends <<";
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--------------------------------------
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--
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--E N D Test_case 06
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--
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--------------------------------------
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--init
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in_imem.read_addr <= (others=>'0');
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in_imem.read_en <= '1';
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wslvi <= wbs_in_none;
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wait for clk_period;
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--end init
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-------------------------------------
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-- Test_case 07:
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--------------------------------------
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-- Sim ins read and data write, non overlap address range
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-- Expected output ins/data is read correctly
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-- Expected error: None
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--
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-- >> data_info
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-- 32b_adr = x"00000215", 30b_adr = x"00000085"
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-- data at the adr = x44303035 (ascii, D005)
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--
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-- >> ins_info
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-- 32b_adr = x"00000052", 30b_adr = x"00000014"
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-- data at the adr = x49303230 (ascii, I020)
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--------------------------------------
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--------------------------------------
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--report ">> TC7 starts <<";
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--------------------------------------
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-- Handshake-1 (in):
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-- data
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tmpadr := x"00000215";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= x"AA35AAAA"; -- feed full data but take written only B2 (feed junk for the rest portion, making sure only sel part is taken)
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wslvi.we <= '1'; -- write
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wslvi.sel <= "0100"; -- sel_byte = B1 -> expected writted data portion = x35
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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-- ins
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in_imem.read_en <= '1'; in_imem.read_addr <= x"00000052";
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wait for clk_period;
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-- Handshake-2 (out):
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-- data
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assert wslvo.ack = '1'
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report"E-70: WR request, ack should be active "
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severity error;
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-- ins
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assert out_imem.read_data = x"49303230" and out_imem.ready = '1' -- overlap address range, ready must be inactive
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report "E-71: imem.ready is inactive or Non-match ins val" &
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" ins_RD req addr: " & hstr(in_imem.read_addr) &
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", Return rd ins val: " & hstr(out_imem.read_data)
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severity error;
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--Read value for checking written value
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-- Handshake-3 (in):
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-- tmpadr := x"00000215";
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-- wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= (others=>'0');
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wslvi.we <= '0'; -- read
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wslvi.sel <= "0100"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x35
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-4 (out):
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assert wslvo.dat = x"00350000" and wslvo.ack = '1'
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report"E-72: wrong data, Return data: " & hstr(wslvo.dat) & " Expected data: " & hstr(x"00350000")
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severity error;
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--------------------------------------
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--report ">> TC7 ends <<";
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--------------------------------------
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--
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--E N D Test_case 07
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--
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--------------------------------------
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--------------------------------------
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-- Test_case 08:
|
|
--------------------------------------
|
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-- Sim ins read and data write, overlap address range
|
|
-- Expected output ins/data is read correctly
|
|
-- Expected error: None
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|
--
|
|
-- >> data_info
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-- 32b_adr = x"00000015", 30b_adr = x"00000005"
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|
-- data at the adr = x49303035 (ascii, I005)
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|
--
|
|
-- >> ins_info
|
|
-- 32b_adr = x"00000052", 30b_adr = x"00000014"
|
|
-- data at the adr = x49303230 (ascii, I020)
|
|
--------------------------------------
|
|
--------------------------------------
|
|
--report ">> TC8 starts <<";
|
|
--------------------------------------
|
|
|
|
-- Handshake-1 (in):
|
|
-- data
|
|
tmpadr := x"00000015";
|
|
wslvi.adr <= tmpadr(31 downto 2);
|
|
wslvi.dat <= x"AA35AAAA"; -- feed full data but take written only B2 (feed junk for the rest portion, making sure only sel part is taken)
|
|
wslvi.we <= '1'; -- write
|
|
wslvi.sel <= "0100"; -- sel_byte = B1 -> expected writted data portion = x35
|
|
wslvi.stb <= '1';
|
|
wslvi.cyc <= '1';
|
|
-- ins
|
|
in_imem.read_en <= '1'; in_imem.read_addr <= x"00000052";
|
|
wait for clk_period;
|
|
|
|
-- Handshake-2 (out):
|
|
-- data
|
|
assert wslvo.ack = '1'
|
|
report"E-80: WR request, No ack "
|
|
severity error;
|
|
-- ins
|
|
assert out_imem.read_data = x"49303230" and out_imem.ready = '0' -- overlap address range, ready must be inactive
|
|
report "E-81: ins_RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
|
|
severity error;
|
|
|
|
--Read value for checking written value
|
|
-- Handshake-3 (in):
|
|
--tmpadr := x"0000000B";
|
|
--wslvi.adr <= tmpadr(31 downto 2);
|
|
wslvi.dat <= (others=>'0');
|
|
wslvi.we <= '0'; -- read
|
|
wslvi.sel <= "0100"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x35
|
|
wslvi.stb <= '1';
|
|
wslvi.cyc <= '1';
|
|
wait for clk_period;
|
|
|
|
-- Handshake-4 (out):
|
|
assert wslvo.dat = x"00350000" and wslvo.ack = '1'
|
|
report"E-82: wrong data, Return data: " & hstr(wslvo.dat) & " Expected data: " & hstr(x"00350000")
|
|
severity error;
|
|
--------------------------------------
|
|
--report ">> TC8 ends <<";
|
|
--------------------------------------
|
|
--
|
|
--E N D Test_case 08
|
|
--
|
|
--------------------------------------
|
|
--/////////////////////////////////////////
|
|
assert false
|
|
report ">>>> Simulation beendet!"
|
|
severity failure;
|
|
--wait;
|
|
end process;
|
|
|
|
END;
|