336 lines
7.4 KiB
VHDL
336 lines
7.4 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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library std;
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use std.standard.all;
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use std.textio.all;
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library work;
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use work.wishbone.all;
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use work.config.all;
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use work.txt_util.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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ENTITY top_tb IS
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END top_tb;
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ARCHITECTURE behavior OF top_tb IS
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--//////////////////////////////////////////////
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--
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-- component
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--
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--//////////////////////////////////////////////
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-- COMPONENT lt16soc_top
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-- PORT(
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-- clk : IN std_logic;
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-- rst : IN std_logic;
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-- led : OUT std_logic_vector(7 downto 0)
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-- );
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-- END COMPONENT;
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--////////////////////////////////////////////
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component wb_intercon
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generic(
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slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"0000_0000_0000_0000";
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mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"0000";
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dat_sz: integer := WB_PORT_SIZE;
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adr_sz: integer := WB_ADR_WIDTH;
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nib_sz: integer := WB_PORT_GRAN
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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msti : out wb_mst_in_vector;
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msto : in wb_mst_out_vector;
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slvi : out wb_slv_in_vector;
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slvo : in wb_slv_out_vector
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);
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end component;
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--////////////////////////////////////////////
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component corewrapper
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generic(
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wbidx: integer := 0
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_imem : in imem_core;
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out_imem : out core_imem;
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in_proc : in irq_core;
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out_proc : out core_irq;
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hardfault : out std_logic;
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wmsti : in wb_mst_in_type;
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wmsto : out wb_mst_out_type
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);
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end component;
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component irq_controller
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_proc : in core_irq;
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out_proc : out irq_core;
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irq_lines : in std_logic_vector((2 ** irq_num_width) - 1 downto 0)
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);
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end component;
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component memwrapper
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generic(
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memaddr : generic_addr_type := CFG_BADR_MEM;
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addrmask : generic_mask_type := CFG_MADR_MEM;
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wbidx : integer := CFG_MEM;
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filename : string := "program.ram";
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dmemsz : integer := DMEMSZ;
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imemsz : integer := IMEMSZ
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic;
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out_byte : out std_logic_vector(7 downto 0);
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end component;
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--///////////////////////////////////////////////
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component wb_stestrd
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generic(
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memaddr : generic_addr_type :=0;
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addrmask : generic_mask_type :=CFG_MADR_FULL;
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wbidx: integer := 0
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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slvi : in wb_slv_in_type;
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slvo : out wb_slv_out_type;
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test_rddat : in std_logic_vector(31 downto 0)
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);
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end component;
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component wb_stestwr
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generic(
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memaddr : generic_addr_type :=0;
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addrmask : generic_mask_type :=CFG_MADR_FULL;
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wbidx: integer := 0
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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slvi : in wb_slv_in_type;
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slvo : out wb_slv_out_type;
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led : out std_logic_vector (7 downto 0)
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);
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end component;
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--//////////////////////////////////////////////
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-- Signals & constants
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--//////////////////////////////////////////////
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constant clk_period : time := 10 ns;
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constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1110_0000_0000_0000";
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constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
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--base adr
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constant CFG_BADR_TSTS1 : generic_addr_type := 16#28400000#; -- 30bits (32b = A1000000)
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constant CFG_BADR_TSTS2 : generic_addr_type := 16#28800000#; -- 30bits (32b = A2000000)
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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--Outputs
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signal led : std_logic_vector(7 downto 0);
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signal out_byte: std_logic_vector(7 downto 0);
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-- Internal signals
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signal irq_lines : std_logic_vector((2 ** irq_num_width) - 1 downto 0) := (others=>'0');
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signal slvo : wb_slv_out_vector := (others=> wbs_out_none);
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signal msto : wb_mst_out_vector := (others=> wbm_out_none);
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signal slvi : wb_slv_in_vector := (others=> wbs_in_none);
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signal msti : wb_mst_in_vector := (others=> wbm_in_none);
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signal core2mem : core_imem;
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signal mem2core : imem_core;
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signal irq2core : irq_core;
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signal core2irq : core_irq;
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signal testslave1_o, testslave2_o: wb_slv_out_type := wbs_out_none;
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signal test_rddat: std_logic_vector(31 downto 0) := (others=>'0');
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begin
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--//////////////////////////////////////////////
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-- Instantiate
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--//////////////////////////////////////////////
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-- uut: lt16soc_top
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-- port map(
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-- clk => clk,
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-- rst => rst,
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-- led => led
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-- );
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wbicn_inst: wb_intercon
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generic map(
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slv_mask_vector => slv_mask_vector,
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mst_mask_vector => mst_mask_vector
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)
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port map(
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clk => clk,
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rst => rst,
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msti => msti,
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msto => msto,
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slvi => slvi,
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slvo => slvo
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);
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corewrap_inst: corewrapper
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generic map(
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wbidx => CFG_LT16
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)
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port map(
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clk => clk,
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rst => rst,
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in_imem => mem2core,
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out_imem => core2mem,
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in_proc => irq2core,
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out_proc => core2irq,
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hardfault => irq_lines(1),
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wmsti => msti(CFG_LT16),
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wmsto => msto(CFG_LT16)
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);
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irqcontr_inst: irq_controller
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port map(
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clk => clk,
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rst => rst,
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in_proc => core2irq,
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out_proc => irq2core,
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irq_lines => irq_lines
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);
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memwrap_inst: memwrapper
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generic map(
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memaddr => CFG_BADR_MEM,
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addrmask => CFG_MADR_MEM,
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wbidx => CFG_MEM,
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filename => "sample-programs\rawhztest.ram",
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dmemsz => DMEMSZ,
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imemsz => IMEMSZ
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)
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port map(
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clk => clk,
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rst => rst,
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in_imem => core2mem,
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out_imem => mem2core,
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fault => irq_lines(2),
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out_byte => out_byte,
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wslvi => slvi(CFG_MEM),
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wslvo => slvo(CFG_MEM)
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);
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srd01: wb_stestrd
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generic map(
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memaddr => CFG_BADR_TSTS1,
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addrmask => CFG_MADR_ZERO,
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wbidx => 1
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)
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port map(
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clk => clk,
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rst => rst,
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slvo => testslave1_o,
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slvi.adr => slvi(1).adr,
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slvi.dat => slvi(1).dat,
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slvi.we => slvi(1).we,
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slvi.sel => slvi(1).sel,
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slvi.stb => slvi(1).stb,
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slvi.cyc => slvi(1).cyc,
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test_rddat => test_rddat
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);
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swr02: wb_stestwr
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generic map(
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memaddr => CFG_BADR_TSTS2,
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addrmask => CFG_MADR_ZERO,
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wbidx => 2
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)
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port map(
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clk => clk,
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rst => rst,
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slvo => testslave2_o,
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slvi.adr => slvi(2).adr,
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slvi.dat => slvi(2).dat,
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slvi.we => slvi(2).we,
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slvi.sel => slvi(2).sel,
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slvi.stb => slvi(2).stb,
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slvi.cyc => slvi(2).cyc,
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led => led
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);
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--//////////////////////////////////////////////
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-- Process
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--//////////////////////////////////////////////
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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reset : process is
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begin
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rst <= '1';
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wait for 3.5 * clk_period;
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rst <= '0';
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wait;
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end process reset;
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irq_stimuli : process is
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begin
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irq_lines(irq_lines'high downto 3) <= (others => '0');
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irq_lines(0) <= '0';
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wait;
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end process irq_stimuli;
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-- -- Stimulus process
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-- stim_proc: process
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-- begin
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-- -- hold reset state for 100 ns.
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-- wait for 100 ns;
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--
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-- wait for clk_period*10;
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--
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-- -- insert stimulus here
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--
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--
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-- wait;
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-- end process;
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end; |