63 lines
1.2 KiB
VHDL
63 lines
1.2 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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entity wb_led is
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generic(
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memaddr : generic_addr_type; --:= CFG_BADR_LED;
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addrmask : generic_mask_type --:= CFG_MADR_LED;
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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led : out std_logic_vector(7 downto 0);
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end wb_led;
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architecture Behavioral of wb_led is
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signal data : std_logic_vector(7 downto 0);
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signal ack : std_logic;
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begin
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process(clk)
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begin
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if clk'event and clk='1' then
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if rst = '1' then
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ack <= '0';
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data <= x"0F";
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else
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if wslvi.stb = '1' and wslvi.cyc = '1' then
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if wslvi.we='1' then
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data <= dec_wb_dat(wslvi.sel,wslvi.dat)(7 downto 0);
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end if;
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if ack = '0' then
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ack <= '1';
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else
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ack <= '0';
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end if;
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else
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ack <= '0';
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end if;
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end if;
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end if;
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end process;
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wslvo.dat(7 downto 0) <= data;
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wslvo.dat(31 downto 8) <= (others=>'0');
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led <= data;
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wslvo.ack <= ack;
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wslvo.wbcfg <= wb_membar(memaddr, addrmask);
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end Behavioral;
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