154 lines
4.3 KiB
VHDL
154 lines
4.3 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use IEEE.math_real.all;
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library work;
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use work.wishbone.all;
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use work.config.all;
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ENTITY wb_intercon IS
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generic(
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slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"0000_0000_0000_0000";
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mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"0000"
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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msti : out wb_mst_in_vector;
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msto : in wb_mst_out_vector;
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slvi : out wb_slv_in_vector;
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slvo : in wb_slv_out_vector
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);
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END ENTITY wb_intercon;
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ARCHITECTURE RTL OF wb_intercon IS
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--selected slv
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signal tmpslvo : wb_slv_out_vector; -- := (others=> wbs_out_none);
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--granted mst
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signal tmpmsto : wb_mst_out_vector; -- := (others=> wbm_out_none);
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signal mgnt_idx : integer range 0 to NWBMST-1;
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signal mgnt : std_logic_vector(0 to NWBMST-1) := (others=>'0');
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signal ssel_idx : integer range 0 to NWBSLV-1;
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signal ssel : std_logic_vector(0 to NWBSLV-1) := (others=>'0');
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BEGIN
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-----------------------------------------------
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-- Master Arbiter: To output which master is granted
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-----------------------------------------------
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mstarb: for i in 0 to NWBMST-1 generate
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onemst: if (i = 0) generate
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onemst_exist: if(mst_mask_vector(i)='1') generate
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tmpmsto(i) <= msto(i) when (msto(i).cyc='1') else
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wbm_out_none;
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end generate onemst_exist;
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onemst_dne: if(mst_mask_vector(i)='0') generate
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tmpmsto(i) <= wbm_out_none;
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end generate onemst_dne;
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end generate onemst;
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mulmst: if (i > 0) generate
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mulmst_exist: if(mst_mask_vector(i)='1') generate
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tmpmsto(i) <= msto(i) when (msto(i).cyc='1') else
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tmpmsto(i-1);
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end generate mulmst_exist;
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mulmst_dne:if(mst_mask_vector(i)='0') generate
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tmpmsto(i) <= tmpmsto(i-1);
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end generate mulmst_dne;
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end generate mulmst;
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end generate mstarb;
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--
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selslv: process(tmpmsto(NWBMST-1) ,slvo, mgnt_idx)
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begin
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slvi <= (others=> wbs_in_none); --init slave_input
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ssel_idx <= 0;
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for i in 0 to NWBSLV-1 loop
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if (slv_mask_vector(i)='1') then
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--slave active and m_req_adr maps to the slave
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if(slvadrmap(slvo(i).wbcfg, tmpmsto(NWBMST-1).adr) and mst_mask_vector(mgnt_idx) = '1') then
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ssel <= (others=>'0'); -- clear gnt for previous grant of lower priority master
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ssel_idx <= i;
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ssel(i) <= '1';
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slvi(i).dat <= tmpmsto(NWBMST-1).dat;
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slvi(i).sel <= tmpmsto(NWBMST-1).sel;
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slvi(i).adr <= tmpmsto(NWBMST-1).adr;
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slvi(i).cyc <= tmpmsto(NWBMST-1).cyc;
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slvi(i).stb <= tmpmsto(NWBMST-1).stb;
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slvi(i).we <= tmpmsto(NWBMST-1).we;
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slvi(i).cti <= tmpmsto(NWBMST-1).cti;
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slvi(i).bte <= tmpmsto(NWBMST-1).bte;
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end if;
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end if;
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end loop;
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end process;
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-----------------------------------
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--slave decoding:
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-----------------------------------
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gen_slvmux: for i in 0 to NWBSLV-1 generate
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-- One slave exists
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oneslv: if (i = 0) generate
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oneslv_exist: if(slv_mask_vector(i)='1') generate
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tmpslvo(i) <= slvo(i) when slvadrmap(slvo(i).wbcfg, tmpmsto(NWBMST-1).adr) else
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wbs_out_none;
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end generate oneslv_exist;
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oneslv_dne: if(slv_mask_vector(i)='0') generate
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tmpslvo(i)<=wbs_out_none;
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end generate oneslv_dne;
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end generate oneslv;
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-- Multiple slaves exists
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mulslv: if (i > 0) generate
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mulslv_exist: if(slv_mask_vector(i)='1') generate
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tmpslvo(i) <= slvo(i) when slvadrmap(slvo(i).wbcfg, tmpmsto(NWBMST-1).adr) else
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tmpslvo(i-1);
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end generate mulslv_exist;
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mulslv_dne: if(slv_mask_vector(i)='0') generate
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tmpslvo(i) <= tmpslvo(i-1);
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end generate mulslv_dne;
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end generate mulslv;
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end generate gen_slvmux;
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gntmst: process(msto)
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begin
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mgnt <= (others=>'0');
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mgnt_idx <= 0;
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for i in 0 to NWBMST-1 loop
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if (mst_mask_vector(i)='1') then
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if(msto(i).cyc='1') then -- check if master still get the bus
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mgnt <= (others=>'0'); -- clear gnt for previous grant of lower priority master
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mgnt_idx <= i;
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mgnt(i) <= '1';
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end if;
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end if;
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end loop;
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end process;
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process(mgnt_idx,tmpslvo(NWBSLV-1).ack,tmpslvo(NWBSLV-1).dat)
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begin
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msti <= (others=> wbm_in_none); --init master_input
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for i in 0 to NWBMST-1 loop
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if mgnt_idx=i then
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msti(i).ack <= tmpslvo(NWBSLV-1).ack;
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else
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msti(i).ack <= '0';
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end if;
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msti(i).dat <= tmpslvo(NWBSLV-1).dat;
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end loop;
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end process;
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END ARCHITECTURE RTL;
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