65 lines
1.2 KiB
VHDL
65 lines
1.2 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY work;
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USE work.lt16soc_peripherals.ALL;
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USE work.wishbone.ALL;
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USE work.wb_tp.ALL;
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USE work.config.ALL;
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ENTITY slvtest IS
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END ENTITY;
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ARCHITECTURE sim OF slvtest IS
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constant CLK_PERIOD : time := 10 ns;
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signal clk : std_logic := '0';
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signal rst : std_logic;
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signal led : std_logic_vector(7 downto 0);
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signal data : std_logic_vector(WB_PORT_SIZE-1 downto 0);
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signal slvi : wb_slv_in_type;
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signal slvo : wb_slv_out_type;
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BEGIN
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SIM_SLV: wb_led
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generic map(
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memaddr => CFG_BADR_LED,
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addrmask => CFG_MADR_LED
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)
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port map(
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clk => clk,
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rst => rst,
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led => led,
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wslvi => slvi,
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wslvo => slvo
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);
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clk_gen: process
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begin
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clk <= not clk;
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wait for CLK_PERIOD/2;
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end process clk_gen;
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stimuli: process
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begin
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rst <= '1';
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wait for CLK_PERIOD;
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rst <= '0';
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data <= std_logic_vector(to_unsigned(431,32));
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wait for CLK_PERIOD;
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generate_sync_wb_single_write(slvi,slvo,clk,data);
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wait for 2 ns;
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data <= (others => '0');
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generate_sync_wb_single_read(slvi,slvo,clk,data);
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wait;
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end process stimuli;
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END ARCHITECTURE;
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