256 lines
6.4 KiB
VHDL
256 lines
6.4 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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library std;
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use std.standard.all;
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use std.textio.all;
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library work;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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use work.txt_util.all;
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use work.wb_tp.all;
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ENTITY mem2wb_tb IS
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END mem2wb_tb;
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ARCHITECTURE behavior OF mem2wb_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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component mem2wb
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generic(
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memaddr : generic_addr_type := CFG_BADR_MEM;
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addrmask : generic_mask_type := CFG_MADR_MEM;
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wbidx : integer := CFG_MEM
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : out core_dmem;
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out_dmem : in dmem_core;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end component;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal out_dmem : dmem_core;
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signal wslvi : wb_slv_in_type := wbs_in_none;
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--Outputs
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signal in_dmem : core_dmem;
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signal wslvo : wb_slv_out_type;
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: mem2wb
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generic map(
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memaddr => CFG_BADR_MEM,
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addrmask => CFG_MADR_MEM,
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wbidx => CFG_MEM
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)
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port map(
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clk => clk,
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rst => rst,
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in_dmem => in_dmem,
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out_dmem => out_dmem,
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wslvi => wslvi,
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wslvo => wslvo
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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reset_process : process
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begin
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--report ">> R e s e t";
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rst <= '1';
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wait for clk_period*3.5;
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rst <= '0';
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wait;
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end process;
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-- Stimulus process
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stim_proc: process
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variable tmpadr :std_logic_vector(memory_width - 1 downto 0) := (others=>'0');
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begin
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--init
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out_dmem.read_data <= (others=>'0');
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out_dmem.ready <= '0';
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--end init
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clk_period*10;
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--------------------------------------
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-- Test_case 00:
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--------------------------------------
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-- No request
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-- Expected output all control signal should be inactive
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-- Expected error: None
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--------------------------------------
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--report ">> TC0 starts <<";
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--------------------------------------
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-- Handshake-1 (in):
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tmpadr := x"0000000B";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= x"49303035";
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wslvi.we <= '0';
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wslvi.sel <= "0001";
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wslvi.stb <= '0';
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wslvi.cyc <= '0';
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wait for clk_period;
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-- Handshake-2 (out):
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assert wb2mem_chk(in_dmem, wslvi, NO_ACC)
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report"E-00: No request, control signal should be inactive"
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severity error;
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-- Handshake-3 (in):
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out_dmem.read_data <= x"00000000"; -- mem always returns data at right most
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out_dmem.ready <= '0';
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wait for clk_period;
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-- Handshake-4 (out):
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assert wslvo.ack = '0'
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report"E-01: No request, ack signal should be inactive"
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severity error;
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--------------------------------------
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--report ">> TC0 ends <<";
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--------------------------------------
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--
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--E N D Test_case 00
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--
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--------------------------------------
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--------------------------------------
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-- Test_case 01:
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--------------------------------------
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-- single read request
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-- given data at addr[0000_00005] = x"49303031"; (ascii = I001)
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-- B0 = x49, B2 = x30, B1 = x30, B0 = x31
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-- Expected output Return correct read data back to wb in correct format
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-- Expected error: None
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--------------------------------------
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--report ">> TC1 starts <<";
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--------------------------------------
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-- Handshake-1 (in):
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tmpadr := x"00000005";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= (others=>'0');
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wslvi.we <= '0'; -- read
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wslvi.sel <= "0100"; -- sel_byte = B1 -> expected value return = 0 (ascii) or x30
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-2 (out):
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assert wb2mem_chk(in_dmem, wslvi, RD_ACC)
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report"E-10: wrong conversion from wb to memory"
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severity error;
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-- Handshake-3 (in):
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out_dmem.read_data <= x"00000030"; -- mem always returns data at right most
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out_dmem.ready <= '1';
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wait for clk_period;
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-- Handshake-4 (out):
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assert wslvo.ack = '1' and wslvo.dat = x"00300000"
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report"E-11: wrong conversion from memory data : " & hstr(out_dmem.read_data) &
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" slvo.data: " & hstr(wslvo.dat)
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severity error;
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--------------------------------------
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--report ">> TC1 ends <<";
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--------------------------------------
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--
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--E N D Test_case 01
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--
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--------------------------------------
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--------------------------------------
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-- Test_case 02:
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--------------------------------------
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-- single write request
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-- given data at addr[0000_0000C] = x"49303035"; (ascii = I005)
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-- B0 = x49, B2 = x30, B1 = x30, B0 = x35
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-- Expected output Return ack, written data is converted correctly
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-- Expected error: None
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--------------------------------------
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--report ">> TC2 starts <<";
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--------------------------------------
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-- Handshake-1 (in):
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tmpadr := x"0000000B";
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wslvi.adr <= tmpadr(31 downto 2);
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wslvi.dat <= x"49303035"; -- feed full data but take written only B2
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wslvi.we <= '1'; -- write
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wslvi.sel <= "0001"; -- sel_byte = B3 -> expected writted data portion = x35
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wslvi.stb <= '1';
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wslvi.cyc <= '1';
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wait for clk_period;
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-- Handshake-2 (out):
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assert wb2mem_chk(in_dmem, wslvi, WR_ACC)
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report"E-20: wrong conversion from wb to memory"
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severity error;
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-- Handshake-3 (in):
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out_dmem.read_data <= x"00000000"; -- mem always returns data at right most
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out_dmem.ready <= '1';
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wait for clk_period;
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-- Handshake-4 (out):
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assert wslvo.ack = '1'
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report"E-21: wrong conversion from memory data : " & hstr(out_dmem.read_data) &
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" slvo.data: " & hstr(wslvo.dat)
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severity error;
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--------------------------------------
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--report ">> TC2 ends <<";
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--------------------------------------
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--
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--E N D Test_case 02
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--
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--------------------------------------
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--clear data
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out_dmem.read_data <= (others=>'0');
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out_dmem.ready <= '0';
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wslvi <= wbs_in_none;
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tmpadr := (others=>'0');
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--end clear
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--/////////////////////////////////////////
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assert false
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report ">>>> Simulation beendet!"
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severity failure;
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--wait;
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end process;
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END;
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