114 lines
2.4 KiB
VHDL
114 lines
2.4 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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library work;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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use work.wb_tp.all;
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ENTITY dmem_test IS
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END dmem_test;
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ARCHITECTURE behavior OF dmem_test IS
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COMPONENT wb_dmem is
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generic(
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memaddr : generic_addr_type;
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addrmask : generic_mask_type := CFG_MADR_DMEM
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal wslvi : wb_slv_in_type := wbs_in_none;
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--Outputs
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signal wslvo : wb_slv_out_type;
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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type block_array is array (0 to 63) of std_logic_vector(7 downto 0);
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type ram_array is array (0 to 3) of block_array;
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constant test_values : ram_array := (
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(x"00", x"04", x"08", others=>x"00"),
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(x"01", x"05", x"09", others=>x"00"),
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(x"02", x"06", x"0a", others=>x"00"),
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(x"03", x"07", x"0b", others=>x"00")
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);
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signal readdata : std_logic_vector(WB_PORT_SIZE -1 downto 0);
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signal writedata : std_logic_vector(WB_PORT_SIZE -1 downto 0);
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: wb_dmem
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generic map(memaddr=>0)
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PORT MAP(clk => clk, rst => rst, wslvi => wslvi, wslvo => wslvo);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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rst <= '1';
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wait for 100 ns;
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rst <= '0';
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wait until falling_edge(clk);
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for i in 0 to 63 loop
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--test 1: write word, read bytes
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-- assume word data is always given in little endian
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writedata <= test_values(3)(i) & test_values(2)(i) & test_values(1)(i) & test_values(0)(i);
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wait until falling_edge(clk);
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generate_async_wb_slave_writeaccess(
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slvi=>wslvi,
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slvo=>wslvo,
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writedata=>writedata
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);
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wait for clk_period;
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for j in 0 to 3 loop
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generate_async_wb_slave_readaccess(
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slvi=>wslvi,
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slvo=>wslvo,
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readdata=>readdata,
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adr_offset=>j,
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size=>"00"
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);
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--wait for 1 ps;
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assert readdata(7 downto 0)=test_values(j)(i) report "Wrong value read!" severity error;
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wait until falling_edge(clk);
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end loop;
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end loop;
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wait for clk_period*10;
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assert false report "Simulation Finished!" severity failure;
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end process;
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END;
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