58 lines
1.0 KiB
VHDL
58 lines
1.0 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY dmem_sw_tb IS
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END ENTITY;
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ARCHITECTURE sim OF dmem_sw_tb IS
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constant CLK_PERIOD : time := 10 ns;
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signal clk : std_logic := '0';
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signal rst : std_logic;
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signal led : std_logic_vector(7 downto 0);
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COMPONENT lt16soc_top IS
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generic(
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programfilename : string := "programs/blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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led : out std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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BEGIN
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dut: lt16soc_top
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generic map(
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programfilename=>"programs/dmem_test.ram"
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)
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port map(
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clk=>clk,
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rst=>rst,
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led=>led
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);
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clk_gen: process
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begin
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clk <= not clk;
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wait for CLK_PERIOD/2;
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end process clk_gen;
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stimuli: process
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begin
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rst <= '0';
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wait for CLK_PERIOD;
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rst <= '1';
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wait for 2000*CLK_PERIOD;
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wait;
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end process stimuli;
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END ARCHITECTURE;
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