344 lines
7.0 KiB
VHDL
344 lines
7.0 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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ENTITY coreicnmem_tb IS
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END coreicnmem_tb;
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ARCHITECTURE behavior OF coreicnmem_tb IS
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--//////////////////////////////////////////////
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-- component
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--//////////////////////////////////////////////
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component core
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port(clk : in std_logic;
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rst : in std_logic;
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stall : in std_logic;
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in_dmem : in dmem_core;
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out_dmem : out core_dmem;
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in_imem : in imem_core;
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out_imem : out core_imem;
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in_irq : in irq_core;
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out_irq : out core_irq;
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hardfault : out std_logic);
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end component core;
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component memdiv
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generic(
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filename : in string := "program.ram";
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size : in integer := 256;
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imem_latency : in time := 5 ns;
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dmem_latency : in time := 5 ns;
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dmemsz : integer := DMEMSZ;
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imemsz : integer := IMEMSZ
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : in core_dmem;
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out_dmem : out dmem_core;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic;
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out_byte : out std_logic_vector(7 downto 0));
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end component;
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component irq_controller
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_proc : in core_irq;
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out_proc : out irq_core;
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irq_lines : in std_logic_vector((2 ** irq_num_width) - 1 downto 0)
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);
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end component;
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component core2wb
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generic(
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wbidx: integer := 0
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : out dmem_core;
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out_dmem : in core_dmem;
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-- wb master port
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wmsti : in wb_mst_in_type;
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wmsto : out wb_mst_out_type
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);
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end component;
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component mem2wb
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generic(
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memaddr : generic_addr_type := 0;
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addrmask : generic_mask_type := 16#3fffff#;
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wbidx : integer := 0
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : out core_dmem;
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out_dmem : in dmem_core;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end component;
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component wb_intercon
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generic(
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slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"0000_0000_0000_0000";
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mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"0000";
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dat_sz: integer := WB_PORT_SIZE;
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adr_sz: integer := WB_ADR_WIDTH;
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nib_sz: integer := WB_PORT_GRAN
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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msti : out wb_mst_in_vector;
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msto : in wb_mst_out_vector;
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slvi : out wb_slv_in_vector;
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slvo : in wb_slv_out_vector
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);
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end component;
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--//////////////////////////////////////////////
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-- signal
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--//////////////////////////////////////////////
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1000_0000_0000_0000";
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constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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-- signals between instances
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signal core2dm_sc : core_dmem;
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signal core2dm_sm : core_dmem;
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signal dm2core_sc : dmem_core;
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signal dm2core_sm : dmem_core;
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signal imem_proc_signal : imem_core;
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signal proc_imem_signal : core_imem;
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signal irq_proc_signal : irq_core;
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signal proc_irq_signal : core_irq;
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signal irq_lines : std_logic_vector((2 ** irq_num_width) - 1 downto 0);
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signal out_byte: std_logic_vector(7 downto 0);
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--signal hardfault: std_logic;
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--signal fault: std_logic;
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----signal slvi : wb_slv_in_type ;--:= wbs_in_none;
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----signal msti : wb_mst_in_type ;--:= wbm_in_none;
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--signal slvo : wb_slv_out_type := wbs_out_none;
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--signal msto : wb_mst_out_type := wbm_out_none;
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signal slvo : wb_slv_out_vector := (others=> wbs_out_none);
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signal msto : wb_mst_out_vector := (others=> wbm_out_none);
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signal slvi : wb_slv_in_vector := (others=> wbs_in_none);
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signal msti : wb_mst_in_vector := (others=> wbm_in_none);
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BEGIN
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--//////////////////////////////////////////////
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-- instantiation
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--//////////////////////////////////////////////
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----------
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--core
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----------
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core_inst : component core
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port map(
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clk => clk,
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rst => rst,
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stall => '0',
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in_dmem => dm2core_sc,
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out_dmem => core2dm_sc,
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in_imem => imem_proc_signal,
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out_imem => proc_imem_signal,
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in_irq => irq_proc_signal,
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out_irq => proc_irq_signal,
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hardfault => irq_lines(1)
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);
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----------
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--memdiv
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----------
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mem_inst: memdiv
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generic map(
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filename => "sample-programs\rawhztest.ram",
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size => DMEMSZ + IMEMSZ,
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imem_latency => 0 ns,
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dmem_latency => 0 ns,
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dmemsz => DMEMSZ,
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imemsz => IMEMSZ
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)
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port map(
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clk => clk,
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rst => rst,
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in_dmem => core2dm_sm,
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out_dmem => dm2core_sm,
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in_imem => proc_imem_signal,
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out_imem => imem_proc_signal,
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fault => irq_lines(2),
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out_byte => out_byte
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);
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----------
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--irq
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----------
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irqcontr_inst: irq_controller
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port map(
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clk => clk,
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rst => rst,
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in_proc => proc_irq_signal,
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out_proc => irq_proc_signal,
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irq_lines => irq_lines
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);
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----------
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--core2wb
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----------
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core2wb0: core2wb
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generic map(
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wbidx => CFG_LT16
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)
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port map(
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clk => clk,
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rst => rst,
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in_dmem => dm2core_sc,
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out_dmem => core2dm_sc,
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wmsti => msti(CFG_LT16),
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wmsto => msto(CFG_LT16)
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);
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----------
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--mem2wb
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----------
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mem2wb0: mem2wb
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generic map(
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memaddr => CFG_BADR_MEM,
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addrmask => CFG_MADR_MEM,
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wbidx => CFG_MEM
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)
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port map(
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clk => clk,
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rst => rst,
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in_dmem => core2dm_sm,
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out_dmem => dm2core_sm,
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wslvi => slvi(CFG_MEM),
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wslvo => slvo(CFG_MEM)
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);
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----------
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--wb_intercon
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----------
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wbicn_inst: wb_intercon
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generic map(
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slv_mask_vector => slv_mask_vector,
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mst_mask_vector => mst_mask_vector
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)
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port map(
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clk => clk,
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rst => rst,
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msti => msti,
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msto => msto,
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slvi => slvi,
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slvo => slvo
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- reset stimuli
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reset : process is
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begin
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rst <= '1';
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wait for 3.5 * clk_period;
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rst <= '0';
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wait;
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end process reset;
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-- irq line stimuli
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irq_stimuli : process is
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begin
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irq_lines(irq_lines'high downto 3) <= (others => '0');
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irq_lines(0) <= '0';
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-- irq0 is reset
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-- irq1 is hardfault
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-- irq2 is memfault
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-- wait for 600 ns;
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-- wait until rising_edge(clk);
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-- irq_lines(3) <= '1';
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-- irq_lines(4) <= '1';
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-- wait until rising_edge(clk);
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-- irq_lines(3) <= '0';
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-- irq_lines(4) <= '0';
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wait;
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end process irq_stimuli;
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-- -- Stimulus process
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-- stim_proc: process
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-- begin
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--
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---- wait for clk_period*10;
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--
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---- slvi.adr <= msto.adr;
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---- slvi.dat <= msto.dat;
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---- slvi.we <= msto.we;
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---- slvi.sel <= msto.sel;
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---- slvi.stb <= msto.stb;
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---- slvi.cyc <= msto.cyc;
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----
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-- ---
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---- msti.dat <= slvo.dat;
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---- msti.ack <= slvo.ack;
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--
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-- wait;
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-- end process;
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END;
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