440 lines
13 KiB
VHDL
440 lines
13 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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library std;
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use std.standard.all;
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use std.textio.all;
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library work;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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use work.txt_util.all;
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use work.wb_tp.all;
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entity core2wb_tb is
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end core2wb_tb;
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architecture behavior of core2wb_tb is
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component core2wb
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : out dmem_core;
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out_dmem : in core_dmem;
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-- wb master port
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wmsti : in wb_mst_in_type;
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wmsto : out wb_mst_out_type
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);
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end component;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal out_dmem : core_dmem;
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signal wmsti : wb_mst_in_type := wbm_in_none;
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--Outputs
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signal in_dmem : dmem_core;
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signal wmsto : wb_mst_out_type;
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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begin
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-- Instantiate the Unit Under Test (UUT)
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uut: core2wb
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port map(
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clk => clk,
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rst => rst,
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in_dmem => in_dmem,
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out_dmem => out_dmem,
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wmsti => wmsti,
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wmsto => wmsto
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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reset_process : process
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begin
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rst <= '1';
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wait for clk_period*3.5;
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rst <= '0';
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wait;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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--gencore2mem_req(out_dmem, req_acc, req_rdadr, req_rdsz, req_wradr, req_wrsz, req_wrdat);
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gencore2mem_req(out_dmem, NO_ACC,
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--rd
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zadr32, "00",
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--wr
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zadr32, "00", dc32);
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--genwb2core(wmsti, req_acc, req_rdsz, wmsto.sel, resp_rddat, READY);
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genwb2core(wmsti, NO_ACC,
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"00", wmsto.sel, dc32, READY);
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wait for clk_period*5;
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--////////////////////////////////////////////
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--------------------------------------
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-- Test_case 00:
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--------------------------------------
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-- No request i.e. quiet test
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-- Expected output wmsto : no response
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-- Expected output in_dmem : no response
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-- Expected error: No error
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--------------------------------------
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-- report ">> TC0 starts <<";
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--------------------------------------
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-- Handshake-1 (in):
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gencore2mem_req(out_dmem, --generated input for core2wbmo_chk
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NO_ACC,
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--rd
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zadr32, "00",
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--wr
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zadr32, "00", dc32);
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wait for clk_period;
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-- Handshake-2 (out):
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--wait for clk_period;
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assert core2wbmo_chk(out_dmem.read_addr, out_dmem.read_size, out_dmem.write_data,
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wmsto, NO_ACC) -- put any address and any size
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report"E-00: msto.stb or msto.cyc should be inactive as there is no request"
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severity error;
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-- Handshake-3 (in):
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genwb2core(wmsti, --generated input for wbmi2core_chk
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NO_ACC, "00", wmsto.sel, dc32, NREADY);
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wait for clk_period;
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-- Handshake-4 (out):
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--wait for clk_period;
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assert wbmi2core_chk(in_dmem,
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NO_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report "E-01: in_dmem.ready not active!"
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severity error;
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--------------------------------------
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--report ">> TC0 ends <<";
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--------------------------------------
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--
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--E N D Test_case 00
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--
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--------------------------------------
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--
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--------------------------------------
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-- Test_case 01:
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--------------------------------------
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-- Single read request
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-- Expected output wmsto : request info from core should be the same as wb request
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-- Expected output in_dmem : resp read_data from wb should be the same as incoming resp data to core module
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-- Expected error: No error
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--------------------------------------
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-- report ">> TC1 starts <<";
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--------------------------------------
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--
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-- test 1A: immediate ack in next clk cycle from request
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--
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-- Handshake-1 (in):
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gencore2mem_req(out_dmem,
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RD_ACC,
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--rd
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x"A1000003", "00",
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--wr
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zadr32, "00", dc32);
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wait for clk_period;
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-- Handshake-2 (out): verify rd and wr addr, wr data, request(stb, cyc)
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assert core2wbmo_chk(out_dmem.read_addr, out_dmem.read_size, out_dmem.write_data,
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wmsto, RD_ACC)
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report"E-10: msto.stb, msto.cyc should be active as there is rd request, and msto.we should = 0 (rd)"
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severity error;
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-- Handshake-3 (in):
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genwb2core(wmsti,
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RD_ACC, "00", wmsto.sel, x"D1AABBCC", READY);
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wait for clk_period;
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-- Handshake-4 (out):
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assert wbmi2core_chk(in_dmem,
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RD_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report "E-11: in_dmem.ready not active or read_data is wrong"
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severity error;
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--
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-- test 1B: Non-immediate ack in next clk cycle from request
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--
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-- Handshake-1 (in):
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gencore2mem_req(out_dmem, --generated input for core2wbmo_chk
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RD_ACC,
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--rd
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x"A1000003", "00",
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--wr
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zadr32, "00", dc32);
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wait for clk_period;
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-- Handshake-2 (out): verify rd and wr addr, wr data, request(stb, cyc)
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assert core2wbmo_chk(out_dmem.read_addr, out_dmem.read_size, out_dmem.write_data,
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wmsto, RD_ACC)
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report"E-12: msto.stb, msto.cyc should be active as there is rd request, and msto.we should = 0 (rd)"
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severity error;
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-- Handshake-3 (in):
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genwb2core(wmsti, --generated input for wbmi2core_chk
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RD_ACC, "00", wmsto.sel, x"D1AABBCC", NREADY);
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wait for clk_period;
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-- Handshake-4 (out):
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assert wbmi2core_chk(in_dmem, RD_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report"E-13: in_dmem.ready always active or read_data is wrong"
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severity error;
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--
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-- test 1C: Different read_size (32b)
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--
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-- Handshake-1 (in):
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--req_rdsz <= "10"; --32b, remark: can't test since read_size has to be the same all the time (fixed in wb_gran)
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gencore2mem_req(out_dmem, --generated input for core2wbmo_chk
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RD_ACC,
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--rd
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x"A1000003", "10", --test diff siz
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--wr
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zadr32, "00", dc32);
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wait for clk_period;
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-- Handshake-2 (out): verify rd and wr addr, wr data, request(stb, cyc)
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assert core2wbmo_chk(out_dmem.read_addr, out_dmem.read_size, out_dmem.write_data,
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wmsto, RD_ACC)
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report"E-14: msto.stb, msto.cyc should be active as there is rd request, and msto.we should = 0 (rd)"
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severity error;
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-- Handshake-3 (in):
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genwb2core(wmsti, --generated input for wbmi2core_chk
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RD_ACC, "10", wmsto.sel, x"D1AABBCC", NREADY);
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wait for clk_period;
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-- Handshake-4 (out):
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assert wbmi2core_chk(in_dmem,
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RD_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report"E-15: in_dmem.ready always active or read_data is wrong"
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severity error;
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--------------------------------------
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--report ">> TC1 ends <<";
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--------------------------------------
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--
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--E N D Test_case 01
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--
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--------------------------------------
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--
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--------------------------------------
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-- Test_case 02:
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--------------------------------------
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-- Single write request
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-- Expected output wmsto : request info from core should be the same as wb request
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-- Expected output in_dmem : get ack
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-- Expected error: No error
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--------------------------------------
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-- report ">> TC2 starts <<";
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--------------------------------------
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--
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-- test 2A: immediate ack in next clk cycle from request
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--
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-- Handshake-1 (in):
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gencore2mem_req(out_dmem, --generated input for core2wbmo_chk
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WR_ACC,
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--rd
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x"A2000000", "00",
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--wr
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x"B2000003", "00", x"DB2200AA");
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wait for clk_period;
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-- Handshake-2 (out):
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assert core2wbmo_chk(out_dmem.write_addr, out_dmem.write_size, out_dmem.write_data,
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wmsto, WR_ACC)
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report"E-20: msto.stb, msto.cyc and msto.we should be active as there is wr request"
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severity error;
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-- Handshake-3 (in):
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genwb2core(wmsti, --generated input for wbmi2core_chk
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WR_ACC, "00", wmsto.sel, x"D2AABBCC", READY);
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wait for clk_period;
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-- Handshake-4 (out):
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assert wbmi2core_chk(in_dmem,
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WR_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report"E-21: in_dmem.ready should be active"
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severity error;
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--
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-- test 2B: Non-immediate ack in next clk cycle from request
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--
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-- Handshake-1 (in):
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gencore2mem_req(out_dmem, --generated input for core2wbmo_chk
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WR_ACC,
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--rd
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x"A2000000", "00",
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--wr
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x"B2000003", "00", x"DB2200AA");
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wait for clk_period;
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-- Handshake-2 (out): verify rd and wr addr, wr data, request(stb, cyc)
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assert core2wbmo_chk(out_dmem.write_addr, out_dmem.write_size, out_dmem.write_data,
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wmsto, WR_ACC)
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report"E-22: msto.stb, msto.cyc and msto.we should be active as there is wr request"
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severity error;
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-- Handshake-3 (in):
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genwb2core(wmsti, --generated input for wbmi2core_chk
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WR_ACC, "00", wmsto.sel, x"D2AABBCC", NREADY);
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-- Handshake-4 (out):
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assert wbmi2core_chk(in_dmem,
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WR_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report"E-23: in_dmem.ready always active or read_data is wrong"
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severity error;
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--
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-- test 2C: Different write_size (32b)
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--
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-- Handshake-1 (in):
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gencore2mem_req(out_dmem, --generated input for core2wbmo_chk
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WR_ACC,
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--rd
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x"A1000003", "00",
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--wr
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x"B2000003", "10", x"DB2200AA");
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wait for clk_period;
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-- Handshake-2 (out): verify rd and wr addr, wr data, request(stb, cyc)
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assert core2wbmo_chk(out_dmem.write_addr, out_dmem.write_size, out_dmem.write_data,
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wmsto, WR_ACC)
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report"E-24: msto.stb, msto.cyc and msto.we should be active as there is wr request"
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severity error;
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-- Handshake-3 (in):
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genwb2core(wmsti, --generated input for wbmi2core_chk
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WR_ACC, "00", wmsto.sel, x"D2AABBCC", NREADY);
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wait for clk_period;
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-- Handshake-4 (out):
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assert wbmi2core_chk(in_dmem,
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WR_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report"E-25: in_dmem.ready always active or read_data is wrong"
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severity error;
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--
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--------------------------------------
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--report ">> TC2 ends <<";
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--------------------------------------
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--
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--E N D Test_case 02
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--
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--------------------------------------
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--
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--------------------------------------
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-- Test_case 03:
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--------------------------------------
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-- Simultaneous request i.e. write and read
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-- Expected output wmsto : request info from core should be the same as wb request
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-- Expected output in_dmem : in_dmem.ready is asserted only when the reading is done but msti.ack should be asserted after both write and read.
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-- Expected error: No error
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--------------------------------------
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-- report ">> TC3 starts <<";
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--------------------------------------
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-- Handshake-1 (in):sim(wr)
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gencore2mem_req(out_dmem, --generated input for core2wbmo_chk
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SIM_ACC,
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--rd
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x"A3000003", "00",
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--wr
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x"B3000001", "00", x"DB3300AA");
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wait for clk_period;
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-------------------------------------------
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-- Handshake-2 (out):wr_req
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assert core2wbmo_chk(out_dmem.write_addr, out_dmem.write_size, out_dmem.write_data,
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wmsto, WR_ACC) -- For simacc, write first
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report"E-30: msto.stb, msto.cyc and msto.we should be active as there is wr request"
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severity error;
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--clear request as we want to test only one sim transaction so far
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out_dmem.write_en <= '0'; out_dmem.read_en <= '0'; wait for clk_period;
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--end tmp clear
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--clear request as we want to test only one sim transaction so far
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--out_dmem.write_en <= '0'; out_dmem.read_en <= '0';
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--end tmp clear
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--wait for 3*clk_period;
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-- Handshake-3 (in):wr_req
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genwb2core(wmsti, --generated input for wbmi2core_chk
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WR_ACC, "00", wmsto.sel, dc32, READY); --READY = out_mem2core.ready (wr is done)
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wait for 0.5*clk_period;
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-- Handshake-4 (out):read req is sent once mem_write is done (mem.ready = 1)
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--wait until wmsti.ack = '1';
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assert wbmi2core_chk(in_dmem,
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SIM_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report"E-31: Sim request (wr)- Wrong ready/ack"
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severity error;
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--//////////////////
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--once wr_ack is sent, wb_intercon should deassert ack = 0 for read request that is just recently sent after wr_req is done
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wmsti.ack <= '0';
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wait for 0.5*clk_period; -- wait for ack to deassert
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--//////////////////
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-- Handshake-5 (out):rd_req
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assert core2wbmo_chk(out_dmem.read_addr, out_dmem.read_size, out_dmem.write_data,
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wmsto, RD_ACC) -- read after write is done
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report"E-32: sim request (rd): msto.stb, msto.cyc and msto.we should be (1, 1, 0)"
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severity error;
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-- Handshake-6 (out):
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genwb2core(wmsti, --generated input for wbmi2core_chk
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RD_ACC, "00", wmsto.sel, x"D3AABBCC", READY);
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wait for clk_period;
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-- Handshake-7 (out):rd_req
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assert wbmi2core_chk(in_dmem,
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RD_ACC, wmsto.sel, wmsti.ack, wmsti.dat)
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report"E-33: wbmi2core_chk function: Wrong read data"
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severity error;
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--------------------------------------
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--report ">> TC3 ends <<";
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--------------------------------------
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--
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--E N D Test_case 03
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--
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--------------------------------------
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--//////////////////////////////////////////////////
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assert false
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report ">>>> Simulation beendet!"
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severity failure;
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end process;
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end;
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