73 lines
4.1 KiB
Verilog
Executable File
73 lines
4.1 KiB
Verilog
Executable File
//////////////////////////////////////////////////////////////////////
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//// ////
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//// can_defines.v ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002, 2003, 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// Uncomment following line if you want to use WISHBONE interface. Otherwise
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// 8051 interface is used.
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`define CAN_WISHBONE_IF
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// Uncomment following line if you want to use CAN in Actel APA devices (embedded memory used)
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// `define ACTEL_APA_RAM
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// Uncomment following line if you want to use CAN in Altera devices (embedded memory used)
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// `define ALTERA_RAM
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// Uncomment following line if you want to use CAN in Xilinx devices (embedded memory used)
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// `define XILINX_RAM
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// Uncomment the line for the ram used in ASIC implementation
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// `define VIRTUALSILICON_RAM
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// `define ARTISAN_RAM
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// Uncomment the following line when RAM BIST is needed (ASIC implementation)
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//`define CAN_BIST // Bist (for ASIC implementation)
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/* width of MBIST control bus */
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//`define CAN_MBIST_CTRL_WIDTH 3
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