382 lines
11 KiB
Verilog
382 lines
11 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// can_btl.v ////
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//// ////
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//// ////
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//// This file is part of the CAN Protocol Controller ////
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//// http://www.opencores.org/projects/can/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Igor Mohor ////
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//// igorm@opencores.org ////
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//// ////
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//// ////
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//// All additional information is available in the README.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002, 2003, 2004 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// The CAN protocol is developed by Robert Bosch GmbH and ////
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//// protected by patents. Anybody who wants to implement this ////
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//// CAN IP core on silicon has to obtain a CAN protocol license ////
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//// from Bosch. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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// `include "timescale.v"
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// synopsys translate_on
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`include "can_defines.v"
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module can_btl
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(
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clk,
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rst,
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rx,
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tx,
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/* Bus Timing 0 register */
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baud_r_presc,
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sync_jump_width,
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/* Bus Timing 1 register */
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time_segment1,
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time_segment2,
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triple_sampling,
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/* Output signals from this module */
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sample_point,
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sampled_bit,
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sampled_bit_q,
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tx_point,
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hard_sync,
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/* Output from can_bsp module */
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rx_idle,
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rx_inter,
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transmitting,
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transmitter,
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go_rx_inter,
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tx_next,
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go_overload_frame,
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go_error_frame,
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go_tx,
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send_ack,
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node_error_passive
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);
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parameter Tp = 1;
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input clk;
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input rst;
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input rx;
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input tx;
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/* Bus Timing 0 register */
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input [5:0] baud_r_presc;
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input [1:0] sync_jump_width;
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/* Bus Timing 1 register */
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input [3:0] time_segment1;
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input [2:0] time_segment2;
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input triple_sampling;
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/* Output from can_bsp module */
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input rx_idle;
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input rx_inter;
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input transmitting;
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input transmitter;
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input go_rx_inter;
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input tx_next;
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input go_overload_frame;
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input go_error_frame;
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input go_tx;
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input send_ack;
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input node_error_passive;
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/* Output signals from this module */
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output sample_point;
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output sampled_bit;
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output sampled_bit_q;
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output tx_point;
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output hard_sync;
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reg [6:0] clk_cnt;
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reg clk_en;
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reg clk_en_q;
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reg sync_blocked;
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reg hard_sync_blocked;
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reg sampled_bit;
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reg sampled_bit_q;
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reg [4:0] quant_cnt;
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reg [3:0] delay;
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reg sync;
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reg seg1;
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reg seg2;
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reg resync_latched;
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reg sample_point;
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reg [1:0] sample;
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reg tx_point;
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reg tx_next_sp;
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wire go_sync;
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wire go_seg1;
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wire go_seg2;
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wire [7:0] preset_cnt;
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wire sync_window;
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wire resync;
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assign preset_cnt = (baud_r_presc + 1'b1)<<1; // (BRP+1)*2
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assign hard_sync = (rx_idle | rx_inter) & (~rx) & sampled_bit & (~hard_sync_blocked); // Hard synchronization
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assign resync = (~rx_idle) & (~rx_inter) & (~rx) & sampled_bit & (~sync_blocked); // Re-synchronization
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/* Generating general enable signal that defines baud rate. */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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clk_cnt <= 7'h0;
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else if (clk_cnt >= (preset_cnt-1'b1))
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clk_cnt <=#Tp 7'h0;
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else
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clk_cnt <=#Tp clk_cnt + 1'b1;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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clk_en <= 1'b0;
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else if ({1'b0, clk_cnt} == (preset_cnt-1'b1))
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clk_en <=#Tp 1'b1;
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else
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clk_en <=#Tp 1'b0;
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end
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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clk_en_q <= 1'b0;
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else
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clk_en_q <=#Tp clk_en;
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end
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/* Changing states */
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assign go_sync = clk_en_q & seg2 & (quant_cnt[2:0] == time_segment2) & (~hard_sync) & (~resync);
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assign go_seg1 = clk_en_q & (sync | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
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assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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tx_point <= 1'b0;
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else
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tx_point <=#Tp ~tx_point & seg2 & ( clk_en & (quant_cnt[2:0] == time_segment2)
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| (clk_en | clk_en_q) & (resync | hard_sync)
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); // When transmitter we should transmit as soon as possible.
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end
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/* When early edge is detected outside of the SJW field, synchronization request is latched and performed when
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SJW is reached */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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resync_latched <= 1'b0;
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else if (resync & seg2 & (~sync_window))
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resync_latched <=#Tp 1'b1;
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else if (go_seg1)
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resync_latched <= 1'b0;
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end
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/* Synchronization stage/segment */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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sync <= 1'b0;
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else if (clk_en_q)
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sync <=#Tp go_sync;
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end
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/* Seg1 stage/segment (together with propagation segment which is 1 quant long) */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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seg1 <= 1'b1;
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else if (go_seg1)
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seg1 <=#Tp 1'b1;
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else if (go_seg2)
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seg1 <=#Tp 1'b0;
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end
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/* Seg2 stage/segment */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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seg2 <= 1'b0;
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else if (go_seg2)
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seg2 <=#Tp 1'b1;
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else if (go_sync | go_seg1)
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seg2 <=#Tp 1'b0;
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end
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/* Quant counter */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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quant_cnt <= 5'h0;
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else if (go_sync | go_seg1 | go_seg2)
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quant_cnt <=#Tp 5'h0;
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else if (clk_en_q)
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quant_cnt <=#Tp quant_cnt + 1'b1;
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end
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/* When late edge is detected (in seg1 stage), stage seg1 is prolonged. */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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delay <= 4'h0;
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else if (resync & seg1 & (~transmitting | transmitting & (tx_next_sp | (tx & (~rx))))) // when transmitting 0 with positive error delay is set to 0
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delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? ({2'h0, sync_jump_width} + 1'b1) : (quant_cnt + 1'b1);
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else if (go_sync | go_seg1)
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delay <=#Tp 4'h0;
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end
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// If early edge appears within this window (in seg2 stage), phase error is fully compensated
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assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
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// Sampling data (memorizing two samples all the time).
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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sample <= 2'b11;
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else if (clk_en_q)
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sample <= {sample[0], rx};
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end
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// When enabled, tripple sampling is done here.
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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begin
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sampled_bit <= 1'b1;
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sampled_bit_q <= 1'b1;
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sample_point <= 1'b0;
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end
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else if (go_error_frame)
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begin
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sampled_bit_q <=#Tp sampled_bit;
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sample_point <=#Tp 1'b0;
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end
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else if (clk_en_q & (~hard_sync))
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begin
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if (seg1 & (quant_cnt == (time_segment1 + delay)))
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begin
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sample_point <=#Tp 1'b1;
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sampled_bit_q <=#Tp sampled_bit;
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if (triple_sampling)
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sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
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else
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sampled_bit <=#Tp rx;
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end
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end
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else
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sample_point <=#Tp 1'b0;
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end
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// tx_next_sp shows next value that will be driven on the TX. When driving 1 and receiving 0 we
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// need to synchronize (even when we are a transmitter)
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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tx_next_sp <= 1'b0;
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else if (go_overload_frame | (go_error_frame & (~node_error_passive)) | go_tx | send_ack)
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tx_next_sp <=#Tp 1'b0;
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else if (go_error_frame & node_error_passive)
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tx_next_sp <=#Tp 1'b1;
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else if (sample_point)
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tx_next_sp <=#Tp tx_next;
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end
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/* Blocking synchronization (can occur only once in a bit time) */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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sync_blocked <=#Tp 1'b1;
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else if (clk_en_q)
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begin
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if (resync)
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sync_blocked <=#Tp 1'b1;
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else if (go_seg2)
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sync_blocked <=#Tp 1'b0;
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end
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end
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/* Blocking hard synchronization when occurs once or when we are transmitting a msg */
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always @ (posedge clk or posedge rst)
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begin
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if (rst)
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hard_sync_blocked <=#Tp 1'b0;
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else if (hard_sync & clk_en_q | (transmitting & transmitter | go_tx) & tx_point & (~tx_next))
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hard_sync_blocked <=#Tp 1'b1;
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else if (go_rx_inter | (rx_idle | rx_inter) & sample_point & sampled_bit) // When a glitch performed synchronization
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hard_sync_blocked <=#Tp 1'b0;
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end
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endmodule
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