150 lines
3.3 KiB
VHDL
150 lines
3.3 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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entity memwrapper is
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generic(
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memaddr : generic_addr_type := CFG_BADR_MEM;
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addrmask : generic_mask_type := CFG_MADR_MEM;
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filename : string := "program.ram";
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size : integer := IMEMSZ
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic;
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--out_byte : out std_logic_vector(7 downto 0);
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-- wb master port
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end entity memwrapper;
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architecture RTL of memwrapper is
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--//////////////////////////////////////////////////////
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-- component
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--//////////////////////////////////////////////////////
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component memdiv
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generic(
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filename : in string := "program.ram";
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size : in integer := IMEMSZ;
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imem_latency : in time := 5 ns;
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dmem_latency : in time := 5 ns
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : in core_dmem;
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out_dmem : out dmem_core;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic
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);
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end component;
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component mem2wb
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generic(
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memaddr : generic_addr_type := CFG_BADR_MEM;
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addrmask : generic_mask_type := CFG_MADR_MEM
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : out core_dmem;
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out_dmem : in dmem_core;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end component;
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--//////////////////////////////////////////////////////
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-- signal
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--//////////////////////////////////////////////////////
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signal outimem : imem_core;
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signal in_dmem : core_dmem;
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signal out_dmem : dmem_core;
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begin
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--//////////////////////////////////////////////////////
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-- Instantiate
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--//////////////////////////////////////////////////////
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mem_inst: memdiv
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generic map(
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filename => filename,
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size => size,
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imem_latency => 1 ns,
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dmem_latency => 1 ns
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)
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port map(
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clk => clk,
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rst => rst,
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in_dmem => in_dmem,
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out_dmem => out_dmem,
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in_imem => in_imem,
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out_imem => outimem,
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fault => fault
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);
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------------------------------------
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-- wb_slv coversion (dmem)
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------------------------------------
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mem2wb_inst: mem2wb
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generic map(
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memaddr => memaddr,
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addrmask => addrmask
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)
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port map(
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clk => clk,
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rst => rst,
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in_dmem => in_dmem,
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out_dmem => out_dmem,
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wslvi => wslvi,
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wslvo => wslvo
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);
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------------------------------------
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-- mem ctrl block
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out_imem.read_data <= outimem.read_data;
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memctrl_reg:process(clk)
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begin
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if rst = '1' then
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out_imem.ready <= '0';
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elsif(rising_edge(clk)) then
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-- TODO: dmem is going to access in imem data portion : how about write ??, can slv overwrite ins (Read only ) ?
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if (in_dmem.read_en = '1' and (to_integer(unsigned(in_dmem.read_addr )) <= IMEMSZ)) or
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(in_dmem.write_en = '1' and (to_integer(unsigned(in_dmem.write_addr)) <= IMEMSZ))
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then
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out_imem.ready <= '0';
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else
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out_imem.ready <= outimem.ready;
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end if;
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end if;
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end process;
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------------------------------------
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-- E N D mem ctrl block
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------------------------------------
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end architecture RTL;
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