61 lines
1.2 KiB
VHDL
61 lines
1.2 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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library work;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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use work.wishbone.all;
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use work.config.all;
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-- package to incorperate memory modules
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package lt16soc_memories is
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--insert components and used functions for the memory modules
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component wb_dmem is
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generic(
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memaddr : generic_addr_type := CFG_BADR_DMEM;
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addrmask : generic_mask_type := CFG_MADR_DMEM
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end component wb_dmem;
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component memwrapper
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generic(
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memaddr : generic_addr_type := CFG_BADR_MEM;
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addrmask : generic_mask_type := CFG_MADR_MEM;
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filename : in string := "programs/program.ram";
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size : in integer := IMEMSZ
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic;
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-- wb slv port
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wslvi : in wb_slv_in_type;
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wslvo : out wb_slv_out_type
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);
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end component;
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end lt16soc_memories;
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package body lt16soc_memories is
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--insert function bodies
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end lt16soc_memories;
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