36 lines
494 B
Plaintext
36 lines
494 B
Plaintext
reset:
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br >main
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nop
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hardfault:
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reti
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nop
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memfault:
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reti
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nop
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.align
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adr_a: .word 0x3C0 // actual adr at mem 0xF0 (0x3C0>>2 bits)
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adr_b: .word 0x3F0 // actual adr at mem 0xFC (0x3F0>>2 bits)
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main:
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ldr r5, >adr_a
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//wait for one cycle after a load is necessary
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nop
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ldr r1, >adr_b
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addi r6,-2
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addi r8, 0x50
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nop
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st32 r5, r6
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//waiting for one cycle when re-accessing a stored value is in accordance with design
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nop
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ld32 r7,r5
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addi r9,0x50
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ld32 r8,r5
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addi r8,1
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st32 r5,r8
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end: br always >end
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nop
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