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lab master WS 20/21

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This commit is contained in:
Johannes Müller
2020-10-27 09:40:16 +01:00
parent 148e0cb892
commit b47cfb5978
11 changed files with 213 additions and 896 deletions
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141
soc/core/core_tb.vhd
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@@ -1,141 +0,0 @@
-- See the file "LICENSE" for the full license governing this code. --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.lt16x32_global.all;
-- this testbench testes the core in total
entity core_tb is
end entity core_tb;
architecture RTL of core_tb is
-- clock period, f = 1/period
constant period : time := 10 ns;
component core
port(clk : in std_logic;
rst : in std_logic;
stall : in std_logic;
in_dmem : in dmem_core;
out_dmem : out core_dmem;
in_imem : in imem_core;
out_imem : out core_imem;
in_irq : in irq_core;
out_irq : out core_irq;
hardfault : out std_logic);
end component core;
component memory
generic(filename : string := "program.ram";
size : integer := 256;
imem_latency : time := 5 ns;
dmem_latency : time := 5 ns);
port(clk : in std_logic;
rst : in std_logic;
in_dmem : in core_dmem;
out_dmem : out dmem_core;
in_imem : in core_imem;
out_imem : out imem_core;
fault : out std_logic;
out_byte : out std_logic_vector(7 downto 0));
end component memory;
component irq_controller
port(clk : in std_logic;
rst : in std_logic;
in_proc : in core_irq;
out_proc : out irq_core;
irq_lines : in std_logic_vector((2 ** irq_num_width) - 1 downto 0));
end component irq_controller;
-- clock signal
signal clk : std_logic := '0';
-- reset signal, active high
signal rst : std_logic := '1';
-- outbyte signal
signal out_byte : std_logic_vector(7 downto 0);
-- signals between instances
signal dmem_proc_signal : dmem_core;
signal proc_dmem_signal : core_dmem;
signal imem_proc_signal : imem_core;
signal proc_imem_signal : core_imem;
signal irq_proc_signal : irq_core;
signal proc_irq_signal : core_irq;
signal irq_lines : std_logic_vector((2 ** irq_num_width) - 1 downto 0);
begin
core_inst : component core
port map(clk => clk,
rst => rst,
stall => '0',
in_dmem => dmem_proc_signal,
out_dmem => proc_dmem_signal,
in_imem => imem_proc_signal,
out_imem => proc_imem_signal,
in_irq => irq_proc_signal,
out_irq => proc_irq_signal,
hardfault => irq_lines(1));
memory_inst : component memory
generic map(--filename => "sample-programs\test_endianess2.ram",
--filename => "sample-programs\rawhztest.ram",
filename => "sample-programs\rdmem.ram",
size => 256,
imem_latency => 0 ns,
dmem_latency => 0 ns)
port map(clk => clk,
rst => rst,
in_dmem => proc_dmem_signal,
out_dmem => dmem_proc_signal,
in_imem => proc_imem_signal,
out_imem => imem_proc_signal,
fault => irq_lines(2),
out_byte => out_byte);
irq_controller_inst : component irq_controller
port map(clk => clk,
rst => rst,
in_proc => proc_irq_signal,
out_proc => irq_proc_signal,
irq_lines => irq_lines);
-- irq line stimuli
irq_stimuli : process is
begin
irq_lines(irq_lines'high downto 3) <= (others => '0');
irq_lines(0) <= '0';
-- irq0 is reset
-- irq1 is hardfault
-- irq2 is memfault
-- wait for 600 ns;
-- wait until rising_edge(clk);
-- irq_lines(3) <= '1';
-- irq_lines(4) <= '1';
-- wait until rising_edge(clk);
-- irq_lines(3) <= '0';
-- irq_lines(4) <= '0';
wait;
end process irq_stimuli;
-- clock stimuli
clock : process is
begin
clk <= not clk;
wait for period / 2;
end process clock;
-- reset stimuli
reset : process is
begin
rst <= '1';
wait for 3.5 * period;
rst <= '0';
wait;
end process reset;
end architecture RTL;

128
soc/core/core_wave.wcfg
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@@ -1,128 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/msys/1.0/home/Ben/hiwi/esysoc/core_tb_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="core_tb" />
<top_module name="lt16x32_global" />
<top_module name="lt16x32_internal" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="textio" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="6" />
<wvobject fp_name="/core_tb/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/out_byte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_byte[7:0]</obj_property>
<obj_property name="ObjectShortName">out_byte[7:0]</obj_property>
</wvobject>
<wvobject fp_name="group35" type="group">
<obj_property name="label">D mem</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/core_tb/dmem_proc_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dmem_proc_signal</obj_property>
<obj_property name="ObjectShortName">dmem_proc_signal</obj_property>
<wvobject fp_name="/core_tb/dmem_proc_signal.read_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_data</obj_property>
<obj_property name="ObjectShortName">dmem_proc_signal.read_data</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/dmem_proc_signal.ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ready</obj_property>
<obj_property name="ObjectShortName">dmem_proc_signal.ready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">proc_dmem_signal</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal</obj_property>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.write_data</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_data</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.write_addr</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_addr</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_size" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.write_size</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_size</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.write_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.write_en</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.write_en</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.read_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_addr</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.read_addr</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.read_size" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_size</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.read_size</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_dmem_signal.read_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.read_en</obj_property>
<obj_property name="ObjectShortName">proc_dmem_signal.read_en</obj_property>
</wvobject>
</wvobject>
</wvobject>
<wvobject fp_name="group34" type="group">
<obj_property name="label">I mem</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/core_tb/imem_proc_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">imem_proc_signal</obj_property>
<obj_property name="ObjectShortName">imem_proc_signal</obj_property>
<wvobject fp_name="/core_tb/imem_proc_signal.read_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_data</obj_property>
<obj_property name="ObjectShortName">imem_proc_signal.read_data</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/imem_proc_signal.ready" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.ready</obj_property>
<obj_property name="ObjectShortName">imem_proc_signal.ready</obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="/core_tb/proc_imem_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">proc_imem_signal</obj_property>
<obj_property name="ObjectShortName">proc_imem_signal</obj_property>
<wvobject fp_name="/core_tb/proc_imem_signal.read_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">.read_addr</obj_property>
<obj_property name="ObjectShortName">proc_imem_signal.read_addr</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_imem_signal.read_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">.read_en</obj_property>
<obj_property name="ObjectShortName">proc_imem_signal.read_en</obj_property>
</wvobject>
</wvobject>
</wvobject>
<wvobject fp_name="group33" type="group">
<obj_property name="label">IRQ</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/core_tb/irq_proc_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">irq_proc_signal</obj_property>
<obj_property name="ObjectShortName">irq_proc_signal</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/proc_irq_signal" type="array" db_ref_id="1">
<obj_property name="ElementShortName">proc_irq_signal</obj_property>
<obj_property name="ObjectShortName">proc_irq_signal</obj_property>
</wvobject>
<wvobject fp_name="/core_tb/irq_lines" type="array" db_ref_id="1">
<obj_property name="ElementShortName">irq_lines[15:0]</obj_property>
<obj_property name="ObjectShortName">irq_lines[15:0]</obj_property>
</wvobject>
</wvobject>
</wave_config>