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fixed issues with the can_tp

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This commit is contained in:
Johannes Müller
2020-07-10 18:14:26 +02:00
parent 94bf35005c
commit 148e0cb892
2 changed files with 21 additions and 88 deletions
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93
soc/lib/can_tp.vhd
View File

@@ -19,25 +19,18 @@ package can_tp is
"000", -- cti
"00" -- bte
);
procedure can_wb_write_reg(
signal wbs_in : out wb_slv_in_type;
signal wbs_out : in wb_slv_out_type;
constant addr : in integer;
constant addr : integer;
constant data : in std_logic_vector(7 downto 0);
signal clk : in std_logic);
procedure can_wb_read_reg(
signal wbs_in : out wb_slv_in_type;
signal wbs_out : in wb_slv_out_type;
constant addr : in integer;
signal clk : in std_logic);
procedure can_wb_read_reg(
signal wbs_in : out wb_slv_in_type;
signal wbs_out : in wb_slv_out_type;
constant addr : in integer;
signal data : out std_logic_vector(7 downto 0);
constant addr : integer;
signal clk : in std_logic);
procedure write_regs_from_file(
@@ -45,12 +38,6 @@ package can_tp is
signal wbs_in : out wb_slv_in_type;
signal wbs_out : in wb_slv_out_type;
signal clk : in std_logic);
-- procedure read_regs_with_fileaddr(
-- constant filename : in string;
-- signal wbs_in : out wb_slv_in_type;
-- signal wbs_out : in wb_slv_out_type;
-- signal clk : in std_logic);
procedure read_regs_with_fileaddr(
constant filename : in string;
@@ -71,13 +58,8 @@ package can_tp is
constant data : std_logic_vector(7 downto 0)
) return std_logic_vector;
function canwb2data(
constant data_in : std_logic_vector(63 downto 0);
constant sel : std_logic_vector(3 downto 0)
) return std_logic_vector;
function can_crc(
constant data: in std_logic_vector(0 to 63);
constant stream_vector: in std_logic_vector(0 to 82);
constant datasize: in integer)return std_logic_vector;
function buildframe(
@@ -89,15 +71,15 @@ package can_tp is
constant tx_frame_pointer: in integer;
constant datasize: in integer;
constant tx_frame: in std_logic_vector(0 to 108)) return std_logic_vector;
procedure set_bit(
signal tx: out std_logic;
constant tx_bit: in std_logic_vector(0 to 4);
constant t_bit: in time;
variable tx_history: inout std_logic_vector(4 downto 0));
variable tx_history: inout std_logic_vector(3 downto 0));
procedure simulate_can_transmission(
constant id : in std_logic_vector(10 to 0);
constant id : in std_logic_vector(10 downto 0);
constant data: in std_logic_vector (0 to 63);
constant datasize: in integer;
constant t_bit: in time;
@@ -149,23 +131,7 @@ package body can_tp is
return wbcan_data;
end data2canwb;
function canwb2data(
constant data_in : std_logic_vector(31 downto 0);
constant sel : std_logic_vector(3 downto 0)
) return std_logic_vector is
variable data_out : std_logic_vector(7 downto 0);
begin
case sel is
when "1000" => data_out := data_in (31 downto 24);
when "0100" => data_out := data_in(23 downto 16);
when "0010" => data_out := data_in(15 downto 8);
when "0001" => data_out := data_in(7 downto 0);
when others => data_out := "0000"; -- should not occour
end case;
return data_out;
end canwb2data;
--does a synchronous wb-single-write-handshake with waitstates and writes to an register of the can controller
--does a asynchronous wb-single-write-handshake and writes to an register of the can controller
procedure can_wb_write_reg(
signal wbs_in : out wb_slv_in_type;
signal wbs_out : in wb_slv_out_type;
@@ -208,6 +174,7 @@ package body can_tp is
wait until wbs_out.ack = '1'; --for 1 ps;
wait until rising_edge(clk);
wbs_in.cyc <= '0';
wbs_in.stb <= '0';
wbs_in.we <= '-';
@@ -215,18 +182,6 @@ package body can_tp is
wbs_in.dat <= (others=>'-');
wbs_in.adr <= (others=>'-');
end can_wb_read_reg;
procedure can_wb_read_reg(
signal wbs_in : out wb_slv_in_type;
signal wbs_out : in wb_slv_out_type;
constant addr : integer;
signal data : out std_logic_vector(7 downto 0);
signal clk : in std_logic) is
begin
can_wb_read_reg(wbs_in, wbs_out, addr, clk);
data <= canwb2data(wbs_out.dat, canint2sel(addr));
end can_wb_read_reg;
@@ -252,27 +207,6 @@ package body can_tp is
end procedure write_regs_from_file;
-- procedure read_regs_with_fileaddr(
-- constant filename : in string;
-- signal wbs_in : out wb_slv_in_type;
-- signal wbs_out : in wb_slv_out_type;
-- signal clk : in std_logic) is
--
-- file sourcefile : text open read_mode is filename;
-- variable input_line : line;
-- variable output_line : line;
-- variable addr : integer;
-- begin
-- while not endfile(sourcefile) loop
-- readline(sourcefile, input_line); --read line
-- read(input_line, addr); --read addr of register
-- can_wb_read_reg(wbs_in, wbs_out, addr, clk);
-- wait for 50 ns;
-- end loop;
-- file_close(sourcefile);
-- end procedure read_regs_with_fileaddr;
procedure read_regs_with_fileaddr(
constant filename : in string;
constant out_filename : in string;
@@ -285,17 +219,18 @@ package body can_tp is
variable input_line : line;
variable output_line : line;
variable addr : integer;
-- variable data : std_logic_vector(7 downto 0);
begin
while not endfile(sourcefile) loop
readline(sourcefile, input_line); --read line
read(input_line, addr); --read addr of register
can_wb_read_reg(wbs_in, wbs_out, addr, clk);
--wait for 1 ns;
wait for 1 ns;
write(output_line,addr);
write(output_line, ' ' );
write(output_line,canwb2data(wbs_out.dat, canint2sel(addr)));
write(output_line,wbs_out.dat);
writeline(targetfile,output_line);
wait for 50 ns;
wait for 49 ns;
end loop;
file_close(sourcefile);
file_close(targetfile);

16
soc/testbench/can_demo_tb.vhd
View File

@@ -51,9 +51,8 @@ architecture RTL of can_demo_tb is
signal wbs_i1 : wb_slv_in_type := wbs_in_default;
signal wbs_o1 : wb_slv_out_type;
signal irq_on1 : std_logic;
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
-- signals to/from controller 2
-- signals to/from controller
signal wbs_i2 : wb_slv_in_type:= wbs_in_default;
signal wbs_o2 : wb_slv_out_type;
signal irq_on2 : std_logic;
@@ -130,11 +129,10 @@ begin
wait on irq_on2;
--read status register of controller 1
can_wb_read_reg(wbs_i1, wbs_o1, 2, data_out ,clk);
can_wb_read_reg(wbs_i1, wbs_o1, 2, clk);
--read from controller 2's read buffer
--read_regs_with_fileaddr("./testdata/data_read.tdf", wbs_i2, wbs_o2, clk);
read_regs_with_fileaddr("./testdata/data_read.tdf", "./results/read_data0.tdf", wbs_i2, wbs_o2, clk);
read_regs_with_fileaddr("./testdata/data_read.tdf", "read_data0.tdf", wbs_i2, wbs_o2, clk);
wait for 1200 ns;
--release receive buffer of controller 2
can_wb_write_reg(wbs_i2, wbs_o2, 1, "00000100", clk);
@@ -148,8 +146,8 @@ begin
wait on irq_on2;
--read from both receive buffers
read_regs_with_fileaddr("./testdata/data_read.tdf", "./results/read_data1.tdf", wbs_i1, wbs_o1, clk);
read_regs_with_fileaddr("./testdata/data_read.tdf", "./results/read_data2.tdf", wbs_i2, wbs_o2, clk);
read_regs_with_fileaddr("./testdata/data_read.tdf", "read_data1.tdf", wbs_i1, wbs_o1, clk);
read_regs_with_fileaddr("./testdata/data_read.tdf", "read_data2.tdf", wbs_i2, wbs_o2, clk);
wait for 2400 ns;
--release both receive buffers
can_wb_write_reg(wbs_i1, wbs_o1, 1, "00000100", clk);
@@ -169,7 +167,7 @@ begin
wait for 10 ns / 2;
end process clock;
-- input files used in this testbench:
-- files used in this testbench:
--
-- default_setup.tdf:
-- 4 00000000