lab master WS 20/21
This commit is contained in:
Johannes Müller
@@ -17,7 +17,7 @@ ARCHITECTURE sim OF warmup1_tb IS
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COMPONENT lt16soc_top IS
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generic(
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programfilename : string := "programs/blinky.ram"
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programfilename : string := "../../programs/blinky.ram"
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);
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port(
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clk : in std_logic;
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315
soc/top/top.ucf
315
soc/top/top.ucf
@@ -1,315 +0,0 @@
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NET clk LOC="AG18";
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NET clk TNM_NET = clk;
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TIMESPEC TS_clk = PERIOD "clk" 10 ns HIGH 50%;
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#reset button (active low)
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NET rst LOC="E7";
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NET rst PULLUP;
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NET rst TIG;
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# LED PINS
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NET led(0) LOC="AG8"; # | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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NET led(1) LOC="AH8"; # | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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NET led(2) LOC="AH9"; # | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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NET led(3) LOC="AG10"; # | IOSTANDARD = LVCMOS18; #LVDCI_18; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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NET led(4) LOC="AH10"; # | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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NET led(5) LOC="AG11"; # | IOSTANDARD = LVCMOS18; #LVDCI_18; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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NET led(6) LOC="AF11"; # | IOSTANDARD = LVCMOS18; #LVDCI_18; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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NET led(7) LOC="AE11"; # | IOSTANDARD = LVCMOS18; #LVDCI_18; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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# LCD PINS
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#NET enableLCD LOC = AA5 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET rsLCD LOC = V7 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET rwLCD LOC = W6 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<7> LOC = AD7 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<6> LOC = AC7 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<5> LOC = AC5 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<4> LOC = AB6 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<3> LOC = AC4 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<2> LOC = AB5 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<1> LOC = AB7 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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#NET dataLCD<0> LOC = Y8 | IOSTANDARD=LVCMOS33 | TIG | PULLDOWN;
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# onBoard SWITCHES
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#NET sw(0) LOC = "J19"; # Bank = 3, Pin name = IO_L3N_GC_3, Sch name = SW0
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#NET sw(1) LOC = "L18"; # Bank = 3, Pin name = IO_L1N_CC_GC_3, Sch name = SW1
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#NET sw(2) LOC = "K18"; # Bank = 3, Pin name = IO_L3P_GC_3, Sch name = SW2
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#NET sw(3) LOC = "H18"; # Bank = 3, Pin name = IO_L0N_CC_GC_3, Sch name = SW3
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#NET sw(4) LOC = "H17"; # Bank = 3, Pin name = IO_L0P_CC_GC_3, Sch name = SW4
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#NET sw(5) LOC = "K17"; # Bank = 3, Pin name = IO_L1P_CC_GC_3, Sch name = SW5
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#NET sw(6) LOC = "G16"; # Bank = 3, Pin name = IO_L2N_GC_VRP_3, Sch name = SW6
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#NET sw(7) LOC = "G15"; # Bank = 3, Pin name = IO_L2P_GC_VRN_3, Sch name = SW7
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# on Board BUTTONS
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#NET "btn<0>" LOC = "G6"; # BTN0
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#NET "btn<1>" LOC = "G7"; # BTN1
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#NET "btn<2>" LOC = "J21"; # BTN3 (joystick button)
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#NET "btn<3>" LOC = "E6"; # Joystick "up"
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#NET "btn<4>" LOC = "K19"; # Joystick "left"
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#NET "btn<5>" LOC = "J17"; # Joystick "right"
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#NET "btn<6>" LOC = "H15"; # Joystick "down"
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# Audio
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#NET "ac97_bitclk" TNM="bitclk" | IOSTANDARD=LVCMOS33 | LOC = "AH17"; # Bank = 4, Pin name = IO_L7P_GC_VRN_4, Sch name = AUD-BIT-CLK
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#NET "ac97_sdi" LOC = "AE18" | IOSTANDARD=LVCMOS33; # Bank = 4, Pin name = IO_L8N_CC_GC_4, Sch name = AUD-SDI
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#NET "ac97_sdo" LOC = "AG20" | IOSTANDARD=LVCMOS33; # Bank = 4, Pin name = IO_L4N_GC_VREF_4, Sch name = AUD-SDO
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#NET "ac97_sync" LOC = "J9" | IOSTANDARD=LVCMOS33; # Bank = 20, Pin name = IO_L9N_CC_20, Sch name = AUD-SYNC
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#NET "ac97_rst" LOC = "E12" | IOSTANDARD=LVCMOS33; # Bank = 20, Pin name = IO_L17P_20, Sch name = AUD-RESET
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#TIMESPEC "TS_AC97_BITCLK"=PERIOD "bitclk" 81.4 ns HIGH 50%;
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##############################################################################################
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# Anything below is unlikely to be used
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##############################################################################################
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#Differential 200MHz CLKs
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#NET clk_200_n LOC="H13";# | IOSTANDARD = LVDS_25; # Bank 3, Vcco=2.5V, No DCI
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#NET clk_200_p LOC="J14";# | IOSTANDARD = LVDS_25; # Bank 3, Vcco=2.5V, No DCI
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#NET rxd1 LOC="AG15" | IOSTANDARD = LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
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#NET txd1 LOC="AF19" | IOSTANDARD = LVCMOS33; # Bank 4, Vcco=3.3V, No DCI
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#NET rxd2 LOC="AF18" | IOSTANDARD = LVCMOS33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET txd2 LOC="AG16" | IOSTANDARD = LVCMOS33; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET ps2_keyb_clk LOC="H9" | IOSTANDARD=LVCMOS33 | PULLUP | SLEW = SLOW | DRIVE = 2;
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#NET ps2_keyb_data LOC="H10" | IOSTANDARD=LVCMOS33 | PULLUP | SLEW = SLOW | DRIVE = 2;
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#NET dvi_iic_scl LOC="U8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET dvi_iic_sda LOC="V8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(0) LOC="G10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(1) LOC="G8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(2) LOC="B12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(3) LOC="D12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(4) LOC="C12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(5) LOC="D11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(6) LOC="F10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(7) LOC="D10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(8) LOC="E9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(9) LOC="F9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(10) LOC="E8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET tft_lcd_data(11) LOC="F8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistor
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#NET tft_lcd_clk_p LOC="K11";
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#NET tft_lcd_clk_n LOC="J11";
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#NET tft_lcd_hsync LOC="H8";
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#NET tft_lcd_vsync LOC="F13";
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#NET tft_lcd_de LOC="V10";
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#NET tft_lcd_reset_b LOC="V9";
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#NET ps2_mouse_clk LOC="R27";# | IOSTANDARD = LVCMOS18; #LVDCI_18; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ps2_mouse_data LOC="U26";# | IOSTANDARD = LVCMOS18; #LVDCI_18; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET phy_col LOC="K6";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_crs LOC="L5";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET PHY_INT LOC="T6"; # Bank 3, Vcco=2.5V, No DCI
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#NET phy_mii_clk LOC="N5";# | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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#NET phy_mii_data LOC="U10";# | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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#NET phy_rst_n LOC="L4";# | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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#NET phy_rx_clk LOC="L19" | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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#NET phy_dv LOC="N8";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_gtx_clk LOC="J20"| IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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#NET phy_rx_data(0) LOC="N7";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_data(1) LOC="R6";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_data(2) LOC="P6";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_data(3) LOC="P5";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_data(4) LOC="M7";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_data(5) LOC="M6";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_data(6) LOC="M5";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_data(7) LOC="L6";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_rx_er LOC="P7";# | IOSTANDARD = LVCMOS33; # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
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#NET phy_tx_clk LOC="J16" | IOSTANDARD = LVCMOS25; # Bank 3, Vcco=2.5V, No DCI
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#NET phy_tx_en LOC="T10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(0) LOC="J5";# | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(1) LOC="G5";# | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(2) LOC="F5";# | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(3) LOC="R7";# | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(4) LOC="T8" ;#| IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(5) LOC="R11" ;#| IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(6) LOC="T11" ;#| IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_data(7) LOC="U7" ;#| IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#NET phy_tx_er LOC="R8" ;#| IOSTANDARD = LVDCI_33 | FAST | DRIVE=8; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
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#DRAM PINS
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#NET ddr_ad(0) LOC="L30";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(1) LOC="M30";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(2) LOC="N29";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(3) LOC="P29";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(4) LOC="K31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(5) LOC="L31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(6) LOC="P31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(7) LOC="P30";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(8) LOC="M31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(9) LOC="R28";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(10) LOC="J31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(11) LOC="R29";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(12) LOC="T31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ad(13) LOC="H29";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#
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#NET ddr_ba(0) LOC="G31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ba(1) LOC="J30";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_ba(2) LOC="R31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#
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#NET ddr_casb LOC="E31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_rasb LOC="H30";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#
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#NET ddr_cke(0) LOC="T28";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_cke(1) LOC="U30";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#
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#NET ddr_clkb(0) LOC="AJ29";# | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_clkb(1) LOC="F28";# | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
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#
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#NET ddr_clk(0) LOC="AK29";# | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_clk(1) LOC="E28";# | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
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#
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#NET ddr_csb(0) LOC="L29";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_csb(1) LOC="J29";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
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#
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#NET ddr_dq(0) LOC="AF30";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(1) LOC="AK31";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(2) LOC="AF31";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(3) LOC="AD30";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(4) LOC="AJ30";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(5) LOC="AF29";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(6) LOC="AD29";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(7) LOC="AE29";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(8) LOC="AH27";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(9) LOC="AF28";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(10) LOC="AH28";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(11) LOC="AA28";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(12) LOC="AG25";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(13) LOC="AJ26";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(14) LOC="AG28";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(15) LOC="AB28";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(16) LOC="AC28";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(17) LOC="AB25";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
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#NET ddr_dq(18) LOC="AC27";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(19) LOC="AA26";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(20) LOC="AB26";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(21) LOC="AA24";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(22) LOC="AB27";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(23) LOC="AA25";# | IOSTANDARD = SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(24) LOC="AC29";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(25) LOC="AB30";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(26) LOC="W31";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(27) LOC="V30";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(28) LOC="AC30";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(29) LOC="W29";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(30) LOC="V27";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(31) LOC="W27";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(32) LOC="V29";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(33) LOC="Y27";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(34) LOC="Y26";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(35) LOC="W24";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(36) LOC="V28";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(37) LOC="W25";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(38) LOC="W26";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(39) LOC="V24";# | IOSTANDARD = SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(40) LOC="R24";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(41) LOC="P25";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(42) LOC="N24";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(43) LOC="P26";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(44) LOC="T24";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(45) LOC="N25";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(46) LOC="P27";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(47) LOC="N28";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(48) LOC="M28";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(49) LOC="L28";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(50) LOC="F25";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(51) LOC="H25";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(52) LOC="K27";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(53) LOC="K28";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(54) LOC="H24";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(55) LOC="G26";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(56) LOC="G25";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(57) LOC="M26";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(58) LOC="J24";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(59) LOC="L26";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(60) LOC="J27";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(61) LOC="M25";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(62) LOC="L25";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dq(63) LOC="L24";# | IOSTANDARD = SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#
|
||||
#NET ddr_dm(0) LOC="AJ31";# | IOSTANDARD = SSTL18_I; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dm(1) LOC="AE28";# | IOSTANDARD = SSTL18_I; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dm(2) LOC="Y24";# | IOSTANDARD = SSTL18_I; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dm(3) LOC="Y31";# | IOSTANDARD = SSTL18_I; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dm(4) LOC="V25";# | IOSTANDARD = SSTL18_I; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dm(5) LOC="P24";# | IOSTANDARD = SSTL18_I; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dm(6) LOC="F26";# | IOSTANDARD = SSTL18_I; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dm(7) LOC="J25";# | IOSTANDARD = SSTL18_I; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#
|
||||
#NET ddr_dqsn(0) LOC="AA30";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(0) LOC="AA29";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsn(1) LOC="AK27";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(1) LOC="AK28";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsn(2) LOC="AJ27";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(2) LOC="AK26";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsn(3) LOC="AA31";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(3) LOC="AB31";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsn(4) LOC="Y29";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(4) LOC="Y28";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsn(5) LOC="E27";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(5) LOC="E26";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsn(6) LOC="G28";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(6) LOC="H28";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsn(7) LOC="H27";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_dqsp(7) LOC="G27";# | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#
|
||||
#NET ddr_odt(0) LOC="F31";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET ddr_odt(1) LOC="F30";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#
|
||||
#NET DDR2_SCL LOC="E29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET DDR2_SDA LOC="F29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#
|
||||
#NET ddr_web LOC="K29";# | IOSTANDARD = SSTL18_I; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
|
||||
#NET DVI_D0 LOC="G10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D1 LOC="G8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D2 LOC="B12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D3 LOC="D12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D4 LOC="C12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D5 LOC="D11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D6 LOC="F10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D7 LOC="D10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D8 LOC="E7"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D9 LOC="F9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D10 LOC="E8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_D11 LOC="F8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_DE LOC="V10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
##NET DVI_GPIO1 LOC="N30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_H LOC="H8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_RESET_B LOC="V9"; # Bank 18, Vcco=3.3V, No DCI
|
||||
#NET DVI_V LOC="F13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_XCLK_N LOC="J11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET DVI_XCLK_P LOC="K11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET FAN_ALERT_B LOC="T30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
|
||||
#NET flash_adv_n LOC="AF21"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors (FLASH_ADV_B)
|
||||
#NET FLASH_AUDIO_RESET_B LOC="AG17"; # Bank 4, Vcco=3.3V, No DCI
|
||||
#NET flash_ce LOC="AE14"; # Bank 2, Vcco=3.3V
|
||||
#NET FLASH_CLK LOC="AG21"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET flash_oen LOC="AF14"; # Bank 2, Vcco=3.3V (FLASH_OE_B)
|
||||
#NET FLASH_WAIT LOC="AH18"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
|
||||
#NET FPGA_AVDD LOC="T18"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_CCLK-R LOC="N15"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_CS_B LOC="N22"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_CS0_B LOC="AF21"; # Bank 2, Vcco=3.3V
|
||||
#NET FPGA_DIFF_CLK_OUT_N LOC="J21"; # Bank 3, Vcco=2.5V, No DCI
|
||||
#NET FPGA_DIFF_CLK_OUT_P LOC="J20"; # Bank 3, Vcco=2.5V, No DCI
|
||||
#NET FPGA_DIN LOC="P15"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_DONE LOC="M15"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_DOUT_BUSY LOC="AD15"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_DX_N LOC="W17"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_DX_P LOC="W18"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_EXP_TCK LOC="AB15"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_EXP_TMS LOC="AC14"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_HSWAPEN LOC="M23"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_INIT_B LOC="N14"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_M0 LOC="AD21"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_M1 LOC="AC22"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_M2 LOC="AD22"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_PROG_B LOC="M22"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_RDWR_B LOC="N23"; # Bank 0, Vcco=3.3V
|
||||
#NET FPGA_ROTARY_INCA LOC="AH30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET FPGA_ROTARY_INCB LOC="AG30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
#NET FPGA_ROTARY_PUSH LOC="AH29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
|
||||
@@ -14,7 +14,7 @@ use work.lt16soc_peripherals.all;
|
||||
|
||||
entity lt16soc_top is
|
||||
generic(
|
||||
programfilename : string := "programs/blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
|
||||
programfilename : string := "../../programs/blinky.ram" -- see "Synthesize XST" process properties for actual value ("-generics" in .xst file)!
|
||||
);
|
||||
port(
|
||||
-- clock signal
|
||||
|
||||
211
soc/top/top.xdc
Normal file
211
soc/top/top.xdc
Normal file
@@ -0,0 +1,211 @@
|
||||
## This file is a general .xdc for the Nexys A7-100T
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];
|
||||
|
||||
|
||||
##Switches
|
||||
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
|
||||
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
|
||||
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
|
||||
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]
|
||||
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
|
||||
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
|
||||
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
|
||||
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7]
|
||||
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8]
|
||||
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9]
|
||||
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
|
||||
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11]
|
||||
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12]
|
||||
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13]
|
||||
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
|
||||
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15]
|
||||
|
||||
## LEDs
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
|
||||
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
|
||||
set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2]
|
||||
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3]
|
||||
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4]
|
||||
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5]
|
||||
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6]
|
||||
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7]
|
||||
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8]
|
||||
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9]
|
||||
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10]
|
||||
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
|
||||
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12]
|
||||
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13]
|
||||
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14]
|
||||
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
|
||||
|
||||
## RGB LEDs
|
||||
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b
|
||||
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g
|
||||
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r
|
||||
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
|
||||
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g
|
||||
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r
|
||||
|
||||
##7 segment display
|
||||
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca
|
||||
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
|
||||
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
|
||||
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd
|
||||
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce
|
||||
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf
|
||||
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg
|
||||
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
|
||||
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
|
||||
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
|
||||
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
|
||||
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
|
||||
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
|
||||
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
|
||||
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
|
||||
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]
|
||||
|
||||
##Buttons
|
||||
set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
|
||||
#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc
|
||||
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu
|
||||
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl
|
||||
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr
|
||||
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd
|
||||
|
||||
|
||||
##Pmod Headers
|
||||
##Pmod Header JA
|
||||
#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1]
|
||||
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2]
|
||||
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3]
|
||||
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4]
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7]
|
||||
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8]
|
||||
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9]
|
||||
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10]
|
||||
|
||||
##Pmod Header JB
|
||||
#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1]
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2]
|
||||
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3]
|
||||
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4]
|
||||
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7]
|
||||
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8]
|
||||
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9]
|
||||
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10]
|
||||
|
||||
##Pmod Header JC
|
||||
#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1]
|
||||
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2]
|
||||
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3]
|
||||
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4]
|
||||
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }]; #IO_L6P_T0_35 Sch=jc[7]
|
||||
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }]; #IO_L22P_T3_35 Sch=jc[8]
|
||||
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9]
|
||||
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10]
|
||||
|
||||
##Pmod Header JD
|
||||
#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1]
|
||||
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2]
|
||||
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3]
|
||||
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4]
|
||||
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7]
|
||||
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8]
|
||||
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9]
|
||||
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10]
|
||||
|
||||
##Pmod Header JXADC
|
||||
#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
|
||||
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
|
||||
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2]
|
||||
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2]
|
||||
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3]
|
||||
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3]
|
||||
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4]
|
||||
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4]
|
||||
|
||||
##VGA Connector
|
||||
#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
|
||||
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
|
||||
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
|
||||
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]
|
||||
#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
|
||||
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
|
||||
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
|
||||
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]
|
||||
#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
|
||||
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1]
|
||||
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
|
||||
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3]
|
||||
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs
|
||||
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs
|
||||
|
||||
##Micro SD Connector
|
||||
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
|
||||
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
|
||||
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
|
||||
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd
|
||||
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0]
|
||||
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1]
|
||||
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2]
|
||||
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]
|
||||
|
||||
##Accelerometer
|
||||
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
|
||||
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
|
||||
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
|
||||
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
|
||||
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
|
||||
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]
|
||||
|
||||
##Temperature Sensor
|
||||
#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
|
||||
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
|
||||
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int
|
||||
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct
|
||||
|
||||
##Omnidirectional Microphone
|
||||
#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk
|
||||
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data
|
||||
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel
|
||||
|
||||
##PWM Audio Amplifier
|
||||
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
|
||||
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
|
||||
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
|
||||
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
|
||||
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
|
||||
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data
|
||||
|
||||
##SMSC Ethernet PHY
|
||||
#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
|
||||
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
|
||||
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
|
||||
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
|
||||
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
|
||||
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
|
||||
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
|
||||
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
|
||||
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
|
||||
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
|
||||
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
|
||||
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
|
||||
|
||||
##Quad SPI Flash
|
||||
#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
|
||||
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
|
||||
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
|
||||
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
|
||||
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
|
||||
@@ -1,579 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<wave_config>
|
||||
<wave_state>
|
||||
</wave_state>
|
||||
<db_ref_list>
|
||||
<db_ref path="C:/msys/1.0/home/Ben/hiwi/esysoc/top_tb_isim_beh.wdb" id="1" type="auto">
|
||||
<top_modules>
|
||||
<top_module name="config" />
|
||||
<top_module name="lt16x32_global" />
|
||||
<top_module name="lt16x32_internal" />
|
||||
<top_module name="math_real" />
|
||||
<top_module name="numeric_std" />
|
||||
<top_module name="std_logic_1164" />
|
||||
<top_module name="std_logic_arith" />
|
||||
<top_module name="textio" />
|
||||
<top_module name="top_tb" />
|
||||
<top_module name="wishbone" />
|
||||
</top_modules>
|
||||
</db_ref>
|
||||
</db_ref_list>
|
||||
<WVObjectSize size="18" />
|
||||
<wvobject fp_name="/top_tb/clk" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">clk</obj_property>
|
||||
<obj_property name="ObjectShortName">clk</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/rst" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">rst</obj_property>
|
||||
<obj_property name="ObjectShortName">rst</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/led" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">led[7:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">led[7:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">slvo[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[15:0]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[15]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[15]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[15]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[15].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[15].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[15].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[15].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[15].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[15].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[15].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[15].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[14]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[14]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[14]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[14].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[14].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[14].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[14].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[14].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[14].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[14].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[14].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[13]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[13]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[13]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[13].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[13].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[13].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[13].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[13].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[13].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[13].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[13].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[12]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[12]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[12]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[12].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[12].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[12].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[12].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[12].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[12].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[12].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[12].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[11]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[11]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[11]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[11].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[11].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[11].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[11].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[11].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[11].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[11].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[11].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[10]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[10]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[10]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[10].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[10].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[10].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[10].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[10].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[10].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[10].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[10].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[9]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[9]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[9]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[9].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[9].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[9].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[9].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[9].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[9].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[9].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[9].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[8]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[8]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[8]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[8].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[8].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[8].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[8].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[8].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[8].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[8].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[8].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[7]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[7]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[7]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[7].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[7].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[7].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[7].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[7].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[7].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[7].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[7].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[6]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[6]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[6]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[6].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[6].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[6].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[6].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[6].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[6].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[6].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[6].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[5]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[5]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[5]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[5].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[5].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[5].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[5].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[5].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[5].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[5].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[5].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[4]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[4]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[4]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[4].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[4].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[4].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[4].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[4].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[4].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[4].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[4].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[3]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[3]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[3]</obj_property>
|
||||
<wvobject fp_name="/top_tb/slvo[3].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[3].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[3].ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[3].ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[3].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[3].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[3].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[3].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[2]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[2]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[2]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[1]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[1]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[1]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvo[0]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[0]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvo[0]</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">msto[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3:0]</obj_property>
|
||||
<wvobject fp_name="/top_tb/msto[3]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[3]</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3]</obj_property>
|
||||
<wvobject fp_name="/top_tb/msto[3].adr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.adr</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].adr</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[3].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[3].we" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.we</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].we</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[3].sel" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.sel</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].sel</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[3].stb" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.stb</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].stb</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[3].cyc" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.cyc</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].cyc</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[3].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[3].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[3].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[2]</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2]</obj_property>
|
||||
<wvobject fp_name="/top_tb/msto[2].adr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.adr</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].adr</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2].we" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.we</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].we</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2].sel" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.sel</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].sel</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2].stb" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.stb</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].stb</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2].cyc" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.cyc</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].cyc</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[2].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[2].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[1]</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1]</obj_property>
|
||||
<wvobject fp_name="/top_tb/msto[1].adr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.adr</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].adr</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1].we" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.we</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].we</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1].sel" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.sel</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].sel</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1].stb" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.stb</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].stb</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1].cyc" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.cyc</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].cyc</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[1].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[1].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0]" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">[0]</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0]</obj_property>
|
||||
<wvobject fp_name="/top_tb/msto[0].adr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.adr</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].adr</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0].dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0].we" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.we</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].we</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0].sel" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.sel</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].sel</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0].stb" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.stb</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].stb</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0].cyc" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.cyc</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].cyc</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0].wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msto[0].wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">msto[0].wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slvi" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">slvi[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">slvi[15:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/msti" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">msti[3:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">msti[3:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/core2mem" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">core2mem</obj_property>
|
||||
<obj_property name="ObjectShortName">core2mem</obj_property>
|
||||
<wvobject fp_name="/top_tb/core2mem.read_addr" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.read_addr</obj_property>
|
||||
<obj_property name="ObjectShortName">core2mem.read_addr</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/core2mem.read_en" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.read_en</obj_property>
|
||||
<obj_property name="ObjectShortName">core2mem.read_en</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/mem2core" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">mem2core</obj_property>
|
||||
<obj_property name="ObjectShortName">mem2core</obj_property>
|
||||
<wvobject fp_name="/top_tb/mem2core.read_data" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.read_data</obj_property>
|
||||
<obj_property name="ObjectShortName">mem2core.read_data</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/mem2core.ready" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ready</obj_property>
|
||||
<obj_property name="ObjectShortName">mem2core.ready</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="group412" type="group">
|
||||
<obj_property name="label">IRQ</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<wvobject fp_name="/top_tb/irq_lines" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">irq_lines[15:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">irq_lines[15:0]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/irq2core" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">irq2core</obj_property>
|
||||
<obj_property name="ObjectShortName">irq2core</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/core2irq" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">core2irq</obj_property>
|
||||
<obj_property name="ObjectShortName">core2irq</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/testslave1_o" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">testslave1_o</obj_property>
|
||||
<obj_property name="ObjectShortName">testslave1_o</obj_property>
|
||||
<wvobject fp_name="/top_tb/testslave1_o.dat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.dat</obj_property>
|
||||
<obj_property name="ObjectShortName">testslave1_o.dat</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/testslave1_o.ack" type="logic" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.ack</obj_property>
|
||||
<obj_property name="ObjectShortName">testslave1_o.ack</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/testslave1_o.wbcfg" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbcfg</obj_property>
|
||||
<obj_property name="ObjectShortName">testslave1_o.wbcfg</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/testslave1_o.wbidx" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">.wbidx</obj_property>
|
||||
<obj_property name="ObjectShortName">testslave1_o.wbidx</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/testslave2_o" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">testslave2_o</obj_property>
|
||||
<obj_property name="ObjectShortName">testslave2_o</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/test_rddat" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">test_rddat[31:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">test_rddat[31:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/slv_mask_vector" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">slv_mask_vector[0:15]</obj_property>
|
||||
<obj_property name="ObjectShortName">slv_mask_vector[0:15]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/mst_mask_vector" type="array" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">mst_mask_vector[0:3]</obj_property>
|
||||
<obj_property name="ObjectShortName">mst_mask_vector[0:3]</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/cfg_badr_tsts1" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">cfg_badr_tsts1</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_badr_tsts1</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/cfg_badr_tsts2" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">cfg_badr_tsts2</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_badr_tsts2</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/top_tb/cfg_madr_zero" type="other" db_ref_id="1">
|
||||
<obj_property name="ElementShortName">cfg_madr_zero</obj_property>
|
||||
<obj_property name="ObjectShortName">cfg_madr_zero</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
Reference in New Issue
Block a user