Clear over CAN working

programs/project.prog

@@ -19,36 +19,55 @@ can_interrupt:
     nop
 
 .align
-led_addr: .word 0x000F0000
-switches_addr: .word 0x000F0004
 dmem_start_addr: .word 0x00000400
 dmem_end_addr: .word 0x000004FC
+
+led_addr: .word 0x000F0000
+switches_addr: .word 0x000F0004
+scrolling_addr: .word 0x000F00A0
+scrolling_count_addr: .word 0x000F00A4
+
 priority_mask: .word 0xFFFFFF03
+write_mask: .word 0x1000000
+clear_mask: .word 0x100
+// scrolling_cnt_value: .word 0x20FC000 // for real board
+scrolling_cnt_value: .word 0x500 // for simulation
 
 // CAN
 can_control_addr: .word 0x000F0100
 can_command_addr: .word 0x000F0101
+can_interrupt_addr: .word 0x000F0103
 can_acceptance_code_addr: .word 0x000F0104
 can_acceptance_mask_addr: .word 0x000F0105
 can_bus_timing0_addr: .word 0x000F0106
 can_bus_timing1_addr: .word 0x000F0107
 can_output_control_addr: .word 0x000F0108
-can_identifier0_addr: .word 0x000F010A
+can_tx_identifier0_addr: .word 0x000F010A
-can_identifier1_addr: .word 0x000F010B
+can_tx_identifier1_addr: .word 0x000F010B
-can_data0_addr: .word 0x000F010C
+can_tx_data0_addr: .word 0x000F010C
-can_data1_addr: .word 0x000F010D
+can_tx_data1_addr: .word 0x000F010D
+can_rx_data0_addr: .word 0x000F0116
+can_rx_data1_addr: .word 0x000F0117
 
 // CAN Constants
 acceptance_code: .word 0x00
 acceptance_mask: .word 0xFF
-// btr0: .word 0x45 Real board
+// btr0: .word 0x45 // for Real board
-// btr1: .word 0x16 Real board
+// btr1: .word 0x16 // for Real board
 btr0: .word 0x80
 btr1: .word 0x48
 output_control: .word 0x02
 control: .word 0xFE
 id0: .word 0xAA
-id1: .word 0xC2
+id1: .word 0xC1 // data length is also encoded here
+rx_interrupt_mask: .word 0x01
+tx_interrupt_mask: .word 0x02
+frame_data_add: .word 0x00
+frame_data_clear: .word 0x01
+frame_frequency: .word 0x02
+button_data_add: .word 0x10000
+button_data_clear: .word 0x20000
+button_frequency: .word 0x40000
 
 main:
     // Initialize stack pointer to the end of the data memory
@@ -58,6 +77,11 @@ main:
     ldr r0, >priority_mask
     and r14, r0, r14
 
+    // (Re)set scrolling speed
+    ldr r5, >scrolling_count_addr
+    ldr r7, >scrolling_cnt_value
+    st32 r5, r7
+
     // --- CAN init ---
     ldr r0, >can_acceptance_code_addr
     ldr r3, >acceptance_code
@@ -83,50 +107,144 @@ main:
     ldr r3, >control
     st08 r0, r3
 
-    ldr r0, >can_identifier0_addr
+loop:
+    br >loop
+    nop
+
+can_interrupt_handler:
+    // Dispatch interrupt event
+    ldr r0, >can_interrupt_addr
+    ld08 r1, r0
+    clr r4
+
+    ldr r2, >rx_interrupt_mask
+    and r5, r1, r2
+    cmp neq r5, r4
+    br true >can_rx_handler
+    nop
+
+    ldr r2, >tx_interrupt_mask
+    and r5, r1, r2
+    cmp neq r5, r4
+    br true >can_tx_handler
+    nop
+
+    // Unimplemented CAN interrupt
+    reti
+    nop
+
+switches_interrupt_handler:
+    // Read switch state
+    ldr r0, >switches_addr
+    ld32 r2, r0
+
+    clr r4
+
+    ldr r3, >button_data_clear
+    and r5, r2, r3
+    cmp neq r5, r4
+    br true >can_send_data_clear_frame
+    nop
+
+    // Unimplemented button function
+    
+    reti
+    nop
+
+can_tx_handler:
+    reti
+    nop
+
+can_send_data_clear_frame:
+    ldr r0, >can_tx_identifier0_addr
     ldr r3, >id0
     st08 r0, r3
 
-    ldr r0, >can_identifier1_addr
+    ldr r0, >can_tx_identifier1_addr
     ldr r3, >id1
     st08 r0, r3
 
-    ldr r0, >can_data0_addr
+    ldr r0, >can_tx_data0_addr
-    clr r3
+    ldr r3, >frame_data_clear
-    addi r3, 0x7A
     st08 r0, r3
 
-    ldr r0, >can_data1_addr
-    clr r3
-    addi r3, 0x4F
-    st08 r0, r3
-
-    // Wait some clks
-    call >wait
-
     ldr r0, >can_command_addr
     clr r3
     addi r3, 0x01
     st08 r0, r3
 
-    ldr r0, >led_addr
-    ldr r1, >switches_addr
-
-    st08 r0, r2
-loop:
-    br >loop
-    nop
-
-switches_interrupt_handler:
-    ld32 r2, r1
-
-    // Set LED to pattern
-    st08 r0, r2
-    
     reti
     nop
 
-can_interrupt_handler:
+can_rx_handler:
+    // Dispatch CAN frame
+    ldr r0, >can_rx_data0_addr
+    ld08 r1, r0
+
+    ldr r2, >frame_data_add
+    cmp eq r2, r1
+    br true >can_handle_data_add_frame
+    nop
+
+    ldr r2, >frame_data_clear
+    cmp eq r2, r1
+    br true >can_handle_data_clear_frame
+    nop
+
+    ldr r2, >frame_frequency
+    cmp eq r2, r1
+    br true >can_handle_frequency_frame
+    nop
+
+    // Unimplemented CAN frame
+    reti
+    nop
+
+.align
+scrolling_addr_ptr: .word =scrolling_addr
+write_mask_ptr: .word =write_mask_ptr
+
+can_handle_data_add_frame:
+    // Expect symbol to add in r10 register
+
+    ldr r0, >scrolling_addr_ptr
+    ld32 r0, r0
+
+    ldr r1, >write_mask_ptr
+    ld32 r1, r1
+
+    lsh r10, r10, 16
+    or r4, r4, r1
+    st32 r0, r4
+
+    reti
+    nop
+
+.align
+clear_mask_ptr: .word =clear_mask
+can_command_addr_ptr: .word =can_command_addr
+
+can_handle_data_clear_frame:
+    // Release receive buffer
+    ldr r0, >can_command_addr_ptr
+    ld32 r0, r0
+    clr r1
+    addi r1, 0x04
+    st08 r0, r1
+
+    ldr r0, >scrolling_addr_ptr
+    ldr r1, >clear_mask_ptr
+
+    ld32 r0, r0
+    ld32 r1, r1
+
+    st32 r0, r1
+
+    reti
+    nop
+
+can_handle_frequency_frame:
+    // TODO
     reti
     nop
 

programs/project_init.prog

@@ -28,6 +28,7 @@ priority_mask: .word 0xFFFFFF03
 // CAN
 can_control_addr: .word 0x000F0100
 can_command_addr: .word 0x000F0101
+can_interrupt_addr: .word 0x000F0103
 can_acceptance_code_addr: .word 0x000F0104
 can_acceptance_mask_addr: .word 0x000F0105
 can_bus_timing0_addr: .word 0x000F0106

soc/testbench/project_2top.vhd

@@ -20,12 +20,14 @@ ARCHITECTURE sim OF project_2top_tb IS
 
 	signal led0	: std_logic_vector(7 downto 0);
     signal led1	: std_logic_vector(7 downto 0);
-    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal btn0 : std_logic_vector(4 downto 0) := (others => '0');
+    signal btn1 : std_logic_vector(4 downto 0) := (others => '0');
     signal sw : std_logic_vector(15 downto 0) := (others => '0');
     signal anodes0 : std_logic_vector(7 downto 0);
     signal cathodes0 : std_logic_vector(7 downto 0);
     signal anodes1 : std_logic_vector(7 downto 0);
     signal cathodes1 : std_logic_vector(7 downto 0);
+    signal rst_n : std_logic;
     
 	constant peer_num_inst : integer := 2;
 	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
@@ -67,7 +69,7 @@ BEGIN
 		clk=>clk,
 		rst=>rst,
 		led=>led0,
-		btn=>btn,
+		btn=>btn0,
 		sw=>sw,
         anodes=>anodes0,
         cathodes=>cathodes0,
@@ -77,13 +79,13 @@ BEGIN
 
     soc1: lt16soc_top
     generic map(
-        programfilename => "../../programs/project_init.ram"
+        programfilename => "../../programs/project.ram"
     )
     port map(
 		clk=>clk,
 		rst=>rst,
 		led=>led1,
-		btn=>btn,
+		btn=>btn1,
 		sw=>sw,
         anodes=>anodes1,
         cathodes=>cathodes1,
@@ -96,7 +98,7 @@ BEGIN
         peer_num => peer_num_inst
     )
     port map(
-        rst => not rst,
+        rst => rst_n,
         rx_vector => rx_vector,
         tx_vector => tx_vector
     );
@@ -112,8 +114,17 @@ BEGIN
 		rst	<= '0';
 		wait for CLK_PERIOD;
 		rst	<= '1';
+		
+		sw <= x"000F";
+		
+		wait for 3us;
+		btn0 <= "00001"; -- add
+		-- btn0 <= "00010"; -- clear
+				
 		wait for 300us;
 		assert false report "Simulation terminated!" severity failure;
 	end process stimuli;
+	
+	rst_n <= not rst;
 
 END ARCHITECTURE;