131 lines
3.0 KiB
VHDL
131 lines
3.0 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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use work.wishbone.all;
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use work.config.all;
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use work.lt16soc_memories.all;
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use work.lt16soc_peripherals.all;
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ENTITY project_2top_tb IS
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END ENTITY;
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ARCHITECTURE sim OF project_2top_tb IS
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constant CLK_PERIOD : time := 10 ns;
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signal clk : std_logic := '0';
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signal rst : std_logic;
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signal led0 : std_logic_vector(7 downto 0);
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signal led1 : std_logic_vector(7 downto 0);
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signal btn0 : std_logic_vector(4 downto 0) := (others => '0');
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signal btn1 : std_logic_vector(4 downto 0) := (others => '0');
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signal sw : std_logic_vector(15 downto 0) := (others => '0');
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signal anodes0 : std_logic_vector(7 downto 0);
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signal cathodes0 : std_logic_vector(7 downto 0);
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signal anodes1 : std_logic_vector(7 downto 0);
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signal cathodes1 : std_logic_vector(7 downto 0);
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signal rst_n : std_logic;
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constant peer_num_inst : integer := 2;
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signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
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signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
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COMPONENT lt16soc_top IS
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generic(
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programfilename : string := "../../programs/project.ram"
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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led : out std_logic_vector(7 downto 0);
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btn : in std_logic_vector(4 downto 0);
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sw : in std_logic_vector(15 downto 0);
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anodes : out std_logic_vector(7 downto 0);
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cathodes : out std_logic_vector(7 downto 0);
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can_rx_i : in std_logic;
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can_tx_o : out std_logic
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);
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END COMPONENT;
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component phys_can_sim
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generic(
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peer_num : integer );
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port(
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rst : in std_logic;
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rx_vector : out std_logic_vector(peer_num - 1 downto 0);
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tx_vector : in std_logic_vector(peer_num - 1 downto 0) );
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end component phys_can_sim;
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BEGIN
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soc0: lt16soc_top
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generic map(
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programfilename => "../../programs/project.ram"
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)
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port map(
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clk=>clk,
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rst=>rst,
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led=>led0,
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btn=>btn0,
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sw=>sw,
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anodes=>anodes0,
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cathodes=>cathodes0,
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can_rx_i=>rx_vector(0),
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can_tx_o=>tx_vector(0)
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);
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soc1: lt16soc_top
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generic map(
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programfilename => "../../programs/project.ram"
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)
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port map(
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clk=>clk,
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rst=>rst,
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led=>led1,
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btn=>btn1,
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sw=>sw,
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anodes=>anodes1,
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cathodes=>cathodes1,
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can_rx_i=>rx_vector(1),
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can_tx_o=>tx_vector(1)
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);
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can_interconnect : phys_can_sim
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generic map(
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peer_num => peer_num_inst
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)
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port map(
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rst => rst_n,
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rx_vector => rx_vector,
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tx_vector => tx_vector
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);
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clk_gen: process
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begin
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clk <= not clk;
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wait for CLK_PERIOD/2;
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end process clk_gen;
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stimuli: process
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begin
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rst <= '0';
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wait for CLK_PERIOD;
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rst <= '1';
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sw <= x"000F";
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wait for 3us;
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btn0 <= "00001"; -- add
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-- btn0 <= "00010"; -- clear
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wait for 300us;
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assert false report "Simulation terminated!" severity failure;
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end process stimuli;
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rst_n <= not rst;
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END ARCHITECTURE;
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