Clear over CAN working

soc/testbench/project_2top.vhd

@@ -20,12 +20,14 @@ ARCHITECTURE sim OF project_2top_tb IS
 
 	signal led0	: std_logic_vector(7 downto 0);
     signal led1	: std_logic_vector(7 downto 0);
-    signal btn : std_logic_vector(4 downto 0) := (others => '0');
+    signal btn0 : std_logic_vector(4 downto 0) := (others => '0');
+    signal btn1 : std_logic_vector(4 downto 0) := (others => '0');
     signal sw : std_logic_vector(15 downto 0) := (others => '0');
     signal anodes0 : std_logic_vector(7 downto 0);
     signal cathodes0 : std_logic_vector(7 downto 0);
     signal anodes1 : std_logic_vector(7 downto 0);
     signal cathodes1 : std_logic_vector(7 downto 0);
+    signal rst_n : std_logic;
     
 	constant peer_num_inst : integer := 2;
 	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
@@ -67,7 +69,7 @@ BEGIN
 		clk=>clk,
 		rst=>rst,
 		led=>led0,
-		btn=>btn,
+		btn=>btn0,
 		sw=>sw,
         anodes=>anodes0,
         cathodes=>cathodes0,
@@ -77,13 +79,13 @@ BEGIN
 
     soc1: lt16soc_top
     generic map(
-        programfilename => "../../programs/project_init.ram"
+        programfilename => "../../programs/project.ram"
     )
     port map(
 		clk=>clk,
 		rst=>rst,
 		led=>led1,
-		btn=>btn,
+		btn=>btn1,
 		sw=>sw,
         anodes=>anodes1,
         cathodes=>cathodes1,
@@ -96,7 +98,7 @@ BEGIN
         peer_num => peer_num_inst
     )
     port map(
-        rst => not rst,
+        rst => rst_n,
         rx_vector => rx_vector,
         tx_vector => tx_vector
     );
@@ -112,8 +114,17 @@ BEGIN
 		rst	<= '0';
 		wait for CLK_PERIOD;
 		rst	<= '1';
+		
+		sw <= x"000F";
+		
+		wait for 3us;
+		btn0 <= "00001"; -- add
+		-- btn0 <= "00010"; -- clear
+				
 		wait for 300us;
 		assert false report "Simulation terminated!" severity failure;
 	end process stimuli;
+	
+	rst_n <= not rst;
 
 END ARCHITECTURE;