Initial Commit
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Thomas Fehmel
319
soc/core/decoder_fsm.vhd
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319
soc/core/decoder_fsm.vhd
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-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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-- the decoder_fsm is the finite state machine handling multi-cycle operation and interrupt acknowledgement
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entity decoder_fsm is
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port(
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-- clock signal
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clk : in std_logic;
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-- reset signal, active high, synchronous
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rst : in std_logic;
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-- stall signal, active high
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stall : in std_logic;
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-- signals from pre-decoder
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in_pre : in pre_fsm;
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-- signals from control path
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in_cp : in cp_dec;
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-- signals from datapath
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in_dp : in dp_dec;
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-- signals to 16bit decoder
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out_16 : out fsm_dec16;
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-- signals to 32bit decoder
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out_32 : out fsm_dec32;
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-- signals to shadow decoder
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out_shd : out fsm_decshd;
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-- signals to decoder mux
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out_mux : out fsm_decmux;
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-- signals to pc counter
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out_pc : out dec_pc;
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-- signals to instruction memory
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out_imem : out dec_imem;
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-- signals from interrupt controller
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in_irq : in irq_dec;
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-- signals to interrupt controller
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out_irq : out dec_irq
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);
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end entity decoder_fsm;
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architecture RTL of decoder_fsm is
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-- possible states of fsm
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type state_type is (normal, reset, reset2, copyPCtoLR, branchdelay, irq_decSP1, irq_pushSR, irq_pushLR, irq_setSR, irq_setPC, reti_popLR, reti_incSP1, reti_popSR, reti_incSP2); --add irq_decSP2 for 4 instruction irq stack solution
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-- current state
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signal state : state_type := normal;
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-- temporary storage for multicycle operations
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signal multicycleinstruction : std_logic_vector(31 downto 0);
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begin
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-- the finite state machine is modelled as mealy-machine
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-- generate output (combinatoric part)
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output : process(in_pre, state, multicycleinstruction, in_cp.condition_holds) is
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variable state_variable : state_type;
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begin
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-- standard output
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out_16.instruction <= nop16;
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out_32.instruction <= in_pre.instruction;
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out_shd.instruction(31 downto 28) <= op_shd_push;
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out_shd.instruction(27 downto 0) <= (others => '0');
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out_mux.mode <= sel_ir16;
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out_pc.stall <= '0';
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out_imem.en <= '1';
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out_irq.ack <= '0';
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out_irq.trap_req <= '0';
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out_irq.trap_num <= (others => '0');
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-- copy state to variable for further processing
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state_variable := state;
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-- don't insert nop in branch delay if no branch taken
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-- happens only, if execute_branch_delay_slot is false
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if ((state = branchdelay) and (in_cp.condition_holds = '0')) then
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state_variable := normal;
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end if;
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-- don't write LR if no call happens
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if ((state = copyPCtoLR) and (in_cp.condition_holds = '0')) then
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state_variable := normal;
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end if;
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-- generate state dependend output
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case state_variable is
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when reset => -- first cycle in reset
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out_pc.stall <= '1';
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out_shd.instruction(31 downto 28) <= op_shd_reset;
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out_mux.mode <= sel_irshadow;
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when reset2 => -- second cycle in reset
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out_pc.stall <= '0';
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out_16.instruction <= nop16;
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out_mux.mode <= sel_ir16;
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when normal => -- standard mode
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out_pc.stall <= '0';
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case in_pre.mode is -- check decoder_pre mode output
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when sel_normal16 => -- normal 16 bit instruction
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out_mux.mode <= sel_ir16;
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out_16.instruction <= in_pre.instruction(15 downto 0);
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when sel_normal32 => -- normal 32 bit instruction
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out_mux.mode <= sel_ir32;
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out_32.instruction <= in_pre.instruction;
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when sel_branch => -- branch instruction
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out_mux.mode <= sel_ir16;
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out_16.instruction <= in_pre.instruction(15 downto 0);
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when sel_call => -- call instruction
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_bct & "01" & in_pre.instruction(9 downto 0);
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--out_imem.en <= '0'; -- imem must be read in case that condition does not hold and next instruction should be executed
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when sel_trap => -- trap instruction
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out_mux.mode <= sel_ir16;
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out_16.instruction <= nop16;
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out_irq.trap_num <= unsigned(in_pre.instruction(irq_num_width - 1 downto 0));
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out_irq.trap_req <= '1';
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when sel_reti => -- reti instruction
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_bct & "0110" & std_logic_vector(lr_num) & "0000";
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out_imem.en <= '0';
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when sel_stall => -- stall (i.e. imem not ready)
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out_mux.mode <= sel_ir16;
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out_16.instruction <= in_pre.instruction(15 downto 0);
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out_pc.stall <= '1';
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end case;
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when copyPCtoLR => -- LR = PC, used in call and irq
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-- only if condition true, else normal instruction (this check is done in state transition)
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_or & std_logic_vector(lr_num) & std_logic_vector(pc_num) & std_logic_vector(pc_num);
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out_imem.en <= '1';
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when branchdelay => -- insert NOP to branch delay slot if enabled in configuration
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out_pc.stall <= '0';
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out_mux.mode <= sel_ir16;
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out_imem.en <= '1';
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--when irq_pushLR => -- irq: push LR
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-- out_pc.stall <= '1';
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-- out_mux.mode <= sel_irshadow;
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-- out_shd.instruction(31 downto 28) <= op_shd_push;
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-- out_shd.instruction(3 downto 0) <= std_logic_vector(lr_num);
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-- out_imem.en <= '0';
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when irq_pushLR =>
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out_pc.stall <= '1';
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_mem & op_mem_st32 & std_logic_vector(sp_num) & std_logic_vector(lr_num);
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out_imem.en <= '1';
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when irq_setSR => -- irq: push SR and set new SR value
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out_pc.stall <= '1';
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out_mux.mode <= sel_irshadow;
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out_shd.instruction(31 downto 28) <= op_shd_setsr;
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-- new runtime priority, other SR flags all zero
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out_shd.instruction(7 downto (8 - irq_prio_width)) <= multicycleinstruction(16 + irq_prio_width - 1 downto 16);
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out_imem.en <= '0';
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when irq_setPC => -- irq: branch to irq address
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out_pc.stall <= '1';
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_bct & "11" & multicycleinstruction(9 downto 0);
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out_imem.en <= '0';
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when reti_popLR => -- reti: load LR from stack
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out_pc.stall <= '0'; --former 1
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_mem & op_mem_ld32 & std_logic_vector(lr_num) & std_logic_vector(sp_num);
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out_imem.en <= '0';
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when reti_popSR => -- reti: load SR from stack
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out_pc.stall <= '1';
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_mem & op_mem_ld32 & std_logic_vector(sr_num) & std_logic_vector(sp_num);
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out_imem.en <= '1';
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when reti_incSP1 => -- reti: increment SP
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out_pc.stall <= '1';
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(4, 8));
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out_imem.en <= '0';
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when reti_incSP2 => -- reti increment SP
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out_pc.stall <= '1';
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(4, 8));
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out_imem.en <= '0';
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when irq_pushSR => -- irq: push SR (store and decrement SP afterwards)
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out_mux.mode <= sel_irshadow;
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out_shd.instruction(31 downto 28) <= op_shd_push;
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out_shd.instruction(3 downto 0) <= std_logic_vector(sr_num);
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out_irq.ack <= '1';
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out_pc.stall <= '1';
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--when irq_pushSR =>
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-- out_pc.stall <= '1';
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-- out_mux.mode <= sel_ir16;
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-- out_16.instruction <= op_mem & op_mem_st32 & std_logic_vector(sp_num) & std_logic_vector(sr_num);
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-- out_imem.en <= '1';
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-- out_irq.ack <= '1';
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when irq_decSP1 =>
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out_pc.stall <= '1';
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out_mux.mode <= sel_ir16;
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out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(-4, 8));
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out_imem.en <= '0';
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--when irq_decSP2 =>
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-- out_pc.stall <= '1';
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-- out_mux.mode <= sel_ir16;
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--out_16.instruction <= op_addi & std_logic_vector(sp_num) & std_logic_vector(to_signed(-4, 8));
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--out_imem.en <= '0';
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end case;
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end process output;
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-- state transition (clocked part)
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state_transition : process(clk) is
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begin
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if (rising_edge(clk)) then
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if (rst = '1') then
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state <= reset;
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elsif (stall = '0') then
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state <= state; -- in default: keep state
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-- check for interrupt request
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if (
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-- not near branch and not in multicycle operation
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(in_pre.mode /= sel_branch) and (state = normal)
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-- interrupt request
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and (in_irq.req = '1')
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-- priority higher than runtime priority or non maskable interrupt
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and ((unsigned(in_irq.priority) > in_dp.runtime_priority) or (in_irq.nmi = '1'))
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) then
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-- in normal mode and irq request
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--state <= irq_pushSR;
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state <= irq_decSP1;
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multicycleinstruction <= (others => '0');
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multicycleinstruction(16 + irq_prio_width - 1 downto 16) <= std_logic_vector(in_irq.priority);
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multicycleinstruction(irq_num_width downto 0) <= std_logic_vector(in_irq.num) & "0";
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-- synthesis translate_off
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assert false report "current runtime priority is " & integer'image(to_integer(in_dp.runtime_priority)) & ". IRQ priority is " & integer'image(to_integer(unsigned(in_irq.priority))) & "." severity note;
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assert false report "handle irq request #" & integer'image(to_integer(unsigned(in_irq.num))) severity note;
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-- synthesis translate_on
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else
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-- no irq request valid
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-- for state transition diagram see documentation
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case state is
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when normal =>
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case in_pre.mode is
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when sel_normal16 =>
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state <= normal;
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when sel_normal32 =>
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state <= normal;
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when sel_call =>
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state <= copyPCtoLR;
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when sel_branch =>
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if (execute_branch_delay_slot) then
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state <= normal;
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else
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state <= branchdelay;
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end if;
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when sel_trap =>
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state <= normal;
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when sel_reti =>
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--state <= reti_incSP1;
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state <= reti_popLR;
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when sel_stall =>
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state <= normal;
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end case;
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when copyPCtoLR =>
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state <= normal;
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when branchdelay =>
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state <= normal;
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--! group by multicycle opertation/pseudo-instruction -TF
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-- i.e. IRQ entry (multicycle)
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when irq_decSP1 =>
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state <= irq_pushSR;
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when irq_pushSR =>
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--state <= irq_decSP2;
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state <= irq_pushLR;
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--when irq_decSP2 =>
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-- state <= irq_pushLR;
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when irq_pushLR =>
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state <= irq_setSR;
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when irq_setSR =>
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state <= irq_setPC;
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when irq_setPC =>
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state <= copyPCtoLR;
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when reti_popLR =>
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state <= reti_incSP1;
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when reti_incSP1 =>
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state <= reti_popSR;
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when reti_popSR =>
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state <= reti_incSP2;
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when reti_incSP2 =>
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state <= normal;
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when reset =>
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state <= reset2;
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when reset2 =>
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state <= normal;
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end case;
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end if;
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end if;
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end if;
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end process state_transition;
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end architecture RTL;
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