Initial Commit

programs/Makefile

@@ -0,0 +1,22 @@
+
+AS=../assembler/asm
+RM= rm -f
+
+SRCS= $(wildcard *.prog)
+OBJS= $(SRCS:.prog=.ram)
+MAPS= $(SRCS:.prog=.map)
+
+all: $(OBJS)
+
+maps: $(MAPS)
+	
+%.ram: %.prog
+	$(AS) $< -o $@
+
+%.map: %.prog
+	$(AS) $< -m $@ -o $*.ram
+
+clean:
+	$(RM) $(OBJS) $(MAPS)
+
+.PHONY: all maps

programs/blinky.prog

@@ -0,0 +1,64 @@
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+addr:
+.word 0x000F0000
+w_cnt_top:	.word 0x1FC000
+//w_cnt_top:	.word 0x1		//for simulation only
+
+main:
+ldr r0,>addr	//LED addr
+addi r6,8		//outer counter top
+clr r7			//wait counter
+ldr r8,>w_cnt_top
+
+out_loop:
+clr r1
+st08 r0,r1
+call >wait
+nop
+
+fill:
+	lsh r1,r1,1
+	addi r1,1
+	st08 r0,r1
+	call >wait
+	nop
+
+	addi r5,1
+	cmp neq r5,r6
+	br true >fill
+	nop
+	clr r5
+
+flush:
+	lsh r1,r1,1
+	st08 r0,r1
+	call >wait
+	nop
+
+	addi r5,1
+	cmp neq r5,r6
+	br true >flush
+	nop
+	clr r5
+	br always >out_loop
+	nop
+
+//subroutine to iterate until counter overflow
+wait:
+	clr r7				//inititalize inner counter
+	inc_i:
+	cmp neq r7,r8
+	br true >inc_i		//if i=cnt_top
+	addi r7,1
+	ret					//else
+	nop

programs/dmem_test.prog

@@ -0,0 +1,165 @@
+//big endian data memory test
+//after the initialization, should the LED become a value differnt from 0, an error occured
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+pointer:
+.word =constants 
+
+constants:
+.word 256
+.word 0x00010203
+.word 0x04040404
+.word 0x000000FF
+
+main:
+	clr r10
+call_1:
+	clr r0	//error msg / state
+	call always >echo_error
+	nop
+	
+	ldr r11,>pointer	
+	ld32 r1,r11	//DMEM addr
+	addi r11,4
+	ld32 r2,r11
+	addi r11,4
+	ld32 r3,r11	//increment
+	addi r11,4
+	ld32 r8,r11	//mask
+
+	addi r11,-12
+
+	//test 1: store 32 bit, load bytes
+test1:
+	mov r4,r2
+	st32 r1,r4
+
+	addi r1,3	//check the LSB first
+
+	ld08 r6,r1	//r6: loaded value
+	and r5,r4,r8	//r5: masked constant
+	cmp neq r5,r6
+	call true >echo_error
+	addi r10,1
+
+	addi r1,-1
+	rsh r4,r4,8
+
+	ld08 r6,r1	//r6: loaded value
+	and r5,r4,r8	//r5: masked constant
+	cmp neq r5,r6
+	call true >echo_error
+	addi r10,1
+
+	addi r1,-1
+	rsh r4,r4,8
+
+	ld08 r6,r1	//r6: loaded value
+	and r5,r4,r8	//r5: masked constant
+	cmp neq r5,r6
+	call true >echo_error
+	addi r10,1
+
+	addi r1,-1
+	rsh r4,r4,8
+
+	ld08 r6,r1	//r6: loaded value
+	and r5,r4,r8	//r5: masked constant
+	cmp neq r5,r6
+	call true >echo_error
+	addi r10,1
+
+	//test 1 end
+
+	add r2,r2,r3
+	addi r1,4
+
+//test 2: store bytes, load word
+test2:
+	mov r4,r2
+	addi r1,3
+
+	st08 r1,r4
+	rsh r4,r4,8
+	addi r1,-1
+	st08 r1,r4
+	rsh r4,r4,8
+	addi r1,-1
+	st08 r1,r4
+	rsh r4,r4,8
+	addi r1,-1
+	st08 r1,r4
+	rsh r4,r4,8
+
+	ld32 r6,r1
+	cmp neq r6,r2
+	call true >echo_error
+	addi r10,1
+
+	ldr r9,>LEDaddr
+	st08 r9,r8
+
+//test 3
+//	prewrite memory with value==baseaddress+offset, 
+//	load 32 bit values and check if correct
+test3:
+	ld32 r1,r11	//DMEM base address
+	add r8,r1,r1 //out-of-range address, incidentally equals baseaddress*2 since baseaddress==length
+	clr r2
+test3_prewrite_mem_loop:
+	st08 r1,r2
+	addi r1,1
+	cmp neq r1,r8
+	br true >test3_prewrite_mem_loop
+	addi r2,1
+	
+	ld32 r1,r11	//DMEM addr
+	addi r11,4
+	ld32 r2,r11	//CMP value
+	addi r11,4
+	ld32 r3,r11	//increment
+	addi r11,-8
+	add r8,r1,r1 //out-of-range address, incidentally equals baseaddress*2 since baseaddress==length
+test3_loop:
+	ld32 r4,r1
+	cmp neq r4,r2
+	call true >echo_error
+	addi r0,1
+	
+	addi r1,4
+	add r2,r2,r3
+	
+	cmp neq r1,r8
+	br true >test3_loop
+	nop
+//end test3
+	
+end:
+	nop
+	br >end
+	nop
+
+.align
+LEDaddr:
+.word 0x000F0000
+
+//expects an error code in r0
+echo_error:
+	nop
+	ldr r9,>LEDaddr
+	st08 r9,r0
+	ret
+	nop
+
+
+
+

programs/example_irq.prog

@@ -0,0 +1,33 @@
+// Interrupt Table
+reset:     br >main
+           nop
+hardfault: br >hardfault_handler
+           nop
+memfault:  br >memfault_handler
+           nop
+irq3:      br >irq3_handler
+           nop
+
+// Main Function
+main:
+           ldr sp, >sp_init
+           clr sr
+
+// endless loop to stop program
+final:
+           br >final
+           nop
+
+// Interrupt Handler
+hardfault_handler:
+           reti
+
+memfault_handler:
+           reti
+
+irq3_handler:
+           reti
+
+// Constant Declaration
+.align
+sp_init:   .word 0x400 // Stackpointer Initial Value

programs/example_led.prog

@@ -0,0 +1,47 @@
+//
+// This program let's the connected LEDs flash
+// with a duty cycle of 50% and
+// a period of approx. 1s
+//
+// r0: counter top
+// r1: counter
+// r2: LED address
+// r3: ones (0xFF)
+// r4: LED values
+
+irq0: br always >main
+nop
+
+// initialization constants
+.align
+sp_init: .word 0x200      // Stack pointer
+top:     .word 16000000   // Counter top
+ptr:     .word 0x0        // pointer to I/O device
+
+// main procedure
+main:
+
+// init registers
+ldr sp, >sp_init
+ldr r0, >top
+ldr r2, >ptr
+clr r1
+clr r3
+clr r4
+addi r3, -1
+
+// loop
+loop:
+
+cmp neq r1, r0
+br true >loop   // loop if not equal (BDS!)
+addi r1, 1      // increment counter
+
+// counter top reached, set LEDs and clear counter
+xor r4, r4, r3  // invert last byte of r4
+st08 r2, r4     // write byte to I/O device
+br always >loop // branch back to loop (BDS!)
+clr r1          // reset counter
+
+nop
+nop

programs/example_minimal.prog

@@ -0,0 +1,2 @@
+reset: br always >reset
+       nop

programs/ld08test.prog

@@ -0,0 +1,19 @@
+addi r0,0x50
+addi r1,7
+st08 r0,r1
+
+nop
+nop
+clr r1
+
+ld08 r2,r0
+
+nop
+nop
+
+st08 r3,r2
+nop
+end:
+nop
+br always >end
+nop

programs/ld16test.prog

@@ -0,0 +1,21 @@
+addi r0,0x50
+addi r1,-3
+nop
+nop
+st16 r0,r1
+
+nop
+nop
+clr r1
+
+ld16 r2,r0
+
+nop
+nop
+
+st16 r3,r2
+nop
+end:
+nop
+br always >end
+nop

programs/ld32test.prog

@@ -0,0 +1,21 @@
+addi r0,0x50
+addi r1,-3
+nop
+nop
+st32 r0,r1
+
+nop
+nop
+clr r1
+
+ld32 r2,r0
+
+nop
+nop
+
+st32 r3,r2
+nop
+end:
+nop
+br always >end
+nop

programs/ldrtest.prog

@@ -0,0 +1,10 @@
+main:
+ldr r0, >dmemaddr
+clr r1
+nop
+st08 r1,r0
+br always >main
+nop
+
+.align
+dmemaddr: .word 0xFFFF

programs/ledtest.prog

@@ -0,0 +1,63 @@
+reset:
+br always >main
+nop
+hardfault:
+reti
+nop
+memfault:
+reti
+nop
+
+.align
+addr:		.word 0x000F0000
+//w_cnt_top:	.word 0x717D7840	//250 ms @ 100MHz
+w_cnt_top:	.word 0x40		//for simulation only
+
+main:
+ldr r0,>addr	//LED addr
+addi r6,8		//outer counter top
+clr r7			//wait counter
+ldr r8,>w_cnt_top
+
+out_loop:
+clr r1
+st08 r0,r1
+call >wait
+nop
+
+fill:
+lsh r1,r1,1
+addi r1,1
+st08 r0,r1
+call >wait
+nop
+
+addi r5,1
+cmp neq r5,r6
+br true >fill
+nop
+clr r5
+
+flush:
+lsh r1,r1,1
+st08 r0,r1
+call >wait
+nop
+
+addi r5,1
+cmp neq r5,r6
+br true >flush
+nop
+clr r5
+br always >out_loop
+nop
+
+//subroutine that iterates until counter overflow
+wait:
+clr r7				//inititalize inner counter
+inc_i:
+cmp neq r7,r8
+br true >inc_i		//if i=cnt_top
+addi r7,1
+reti 				//else
+nop

programs/new.prog

@@ -0,0 +1,30 @@
+addi r0,0
+addi r1,0
+addi r2,127
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+add r2,r2,r2
+
+addi r3,7
+st08 r0,r3
+clr r3
+
+loopout:
+loopin:
+addi r1,1
+cmp neq r2,r1
+br true >loopin
+nop
+
+clr r1
+addi r3,1
+st08 r0,r3
+br always >loopout
+nop

programs/rawhztest.prog

@@ -0,0 +1,35 @@
+reset: 
+br >main
+nop
+hardfault: 
+reti
+nop
+memfault: 
+reti
+nop
+
+.align
+adr_a:	.word	0x3C0	// actual adr at mem 0xF0 (0x3C0>>2 bits)
+adr_b:	.word	0x3F0	// actual adr at mem 0xFC (0x3F0>>2 bits)
+
+main:
+ldr r5, >adr_a
+//wait for one cycle after a load is necessary
+nop
+ldr r1, >adr_b
+
+addi r6,-2
+addi r8, 0x50
+nop
+
+st32 r5, r6
+//waiting for one cycle when re-accessing a stored value is in accordance with design
+nop
+ld32 r7,r5
+addi r9,0x50
+ld32 r8,r5
+addi r8,1
+st32 r5,r8
+
+end: br always >end
+nop

programs/rdins.prog

@@ -0,0 +1,29 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+
+.align
+adr_a:	.word	0x3C0	//  (30b adr), actual adr at mem 0xF00 (0x3C0<<2 bits)
+adr_b:	.word	0x3F0	//  (30b adr), actual adr at mem 0xFC0 (0x3F0<<2 bits)
+
+
+main:
+clr r0
+clr r1
+clr r2
+clr r3
+
+//------------------------------
+// read only ins test
+//------------------------------
+
+addi r1, 0x01	//expected r1 = 0x01
+addi r2, 0x02	//expected r1 = 0x02
+add r0, r1, r2	// expected r0 = 0x03
+add r3, r0, r1	// expected r3 = 3 + 1 = 0x4
+
+end: br always >end
+nop

programs/rdmem.prog

@@ -0,0 +1,31 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+
+.align
+adr_i0:	.word	0x001	//  (30b adr), actual adr at mem 0x004 (0x001<<2 bits)
+adr_a:	.word	0x3C0	//  (30b adr), actual adr at mem 0xF00 (0x3C0<<2 bits)
+adr_b:	.word	0x3F0	//  (30b adr), actual adr at mem 0xFC0 (0x3F0<<2 bits)
+
+
+main:
+clr r0
+clr r1
+clr r2
+clr r3
+
+//------------------------------
+// read only mem from ins addr range
+//------------------------------
+addi r3, 0x10 //32 bit adr 
+ld32 r0, r3 // val at addr 0x04 (30 bits) = 0x000003C0 (b0 = x00, b1 = x00, b2 = x03, b3 = xC0)
+add r1, r0, r0 //expected r1 = 0x3C0 + 0x3C0 = 780
+
+addi r4, 0x12 
+ld08 r5, r4	// get Byte2, r5 = 0x03
+
+end: br always >end
+nop

programs/rdwrmem.prog

@@ -0,0 +1,33 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+
+.align
+adr_a:		.word	0x3C0	//  (30b adr), actual adr at mem 0xF00 (0x3C0<<2 bits)
+adr_b:		.word	0x3F0	//  (30b adr), actual adr at mem 0xFC0 (0x3F0<<2 bits)
+adr_c:		.word	0x09
+
+main:
+//------------------------------
+// read only mem from ins addr range
+//------------------------------
+addi r3, 0x10 //32 bit adr 
+ld32 r0, r3 // val at addr 0x04 (30 bits) = 0x000003C0 (b0 = x00, b1 = x00, b2 = x03, b3 = xC0)
+add r1, r0, r0 //expected r1 = 0x3C0 + 0x3C0 = 780
+
+addi r4, 0x12 
+ld08 r5, r4	// get Byte2, r5 = 0x03
+
+//------------------------------
+// write mem test
+//------------------------------
+addi r8, 0x77
+addi r7, 0x51 //32 bit adr , write to Byte 1 > xx77_xxxx at mem[0x14]
+st08 r7, r8
+
+
+end: br always >end
+nop

programs/simple.prog

@@ -0,0 +1,35 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+
+main: // actual start of program
+
+clr r0
+clr r1
+clr r2
+clr r3
+clr r4
+
+//test move = or
+addi r0, 0x55		// expected r0 = 0x55
+mov r1, r0			// expected r1 = 0x55
+
+//test shift
+addi r2, 0x0A		//expected r2 = 0x0A
+lsh	r3, r2, 16		//expected r3 = 0xA_0000
+lsh	r3, r3, 12		//expected r3 = 0xA000_0000
+
+// test write
+ldr r4, >adr_a		//expected r4 = 0x3C0
+st32 r4, r3			//expected value at addr 0xF00 = 0xA000_0000
+
+end: br always >end
+nop
+
+		.align
+adr_a:	.word	0x3C0	// actual adr at mem 0xF00 (0x3C0<<2 bits)
+//adr_a:	.word	0x3F8
+//adr_a:	.word	0x20C

programs/subseqtest.prog

@@ -0,0 +1,43 @@
+reset:
+	br always >main
+	nop
+
+hardfault:
+	br always >main
+	reti
+
+memfault:
+	br always >main
+	reti
+
+.align
+t1: 	.word 0xA0B0C0D0
+t2: 	.word 0xF0AB2FB9
+t3: 	.word 0xCCCCCCCC
+adr1:	.word 0x150
+adr2:	.word 0x144
+adr3:	.word 0x10F
+
+main:
+	ldr r1, >adr1
+	ldr r2, >adr2
+	ldr r3, >adr3
+
+	addi r0,-1
+
+	ldr r4,>t1
+	st16 r1,r0	//mem() = 0x0000FFFF
+	st08 r2,r0	//mem() = 0x000000FF
+	st32 r3,r0	//mem() = 0xFFFFFFFF
+	ldr r11,>t1
+	ldr r10,>t2
+	ldr r9,>t3
+	ldr r7,>t1
+	ldr r6,>t2
+	ld16 r11,r1
+	ld08 r10,r2
+	ld32 r9,r3
+
+end:
+	br always >end
+	nop

programs/test-trap.prog

@@ -0,0 +1,39 @@
+irq0: 
+br always >main
+nop
+irq1: 
+br always >irq
+nop
+irq2: 
+br always >irq
+nop
+
+
+main: 
+ldr sp, >sp_init
+nop 
+clr sr
+
+addi r2, 1
+addi r2, 2
+addi r2, 3
+trap 1
+addi r2, 4
+addi r2, 5
+
+loop:
+addi r10, 1
+foo: br always >loop
+nop
+
+end: br always >end
+nop
+
+irq: addi r0, 5
+reti
+nop
+
+.address 100
+.word 499
+sp_init: .word 500
+.word 501

programs/test.prog

@@ -0,0 +1,46 @@
+//
+// This program let's the connected LEDs flash
+// with a duty cycle of 50%.
+//
+// r0: counter top
+// r1: counter
+// r2: LED address
+// r3: ones (0xFF)
+// r4: LED values
+
+irq0: br always >main
+nop
+
+// initialization constants
+.align
+sp_init: .word 0x200      // Stack pointer
+top:     .word 160000     // Counter top
+ptr:     .word 0x0        // pointer to I/O device
+
+// main procedure
+main:
+
+// init registers
+ldr sp, >sp_init
+ldr r0, >top
+ldr r2, >ptr
+clr r1
+clr r3
+clr r4
+addi r3, -1
+
+// loop
+loop:
+
+cmp neq r1, r0
+br true >loop   // loop if not equal (BDS!)
+addi r1, 1      // increment counter
+
+// counter top reached, set LEDs and clear counter
+xor r4, r4, r3  // invert last byte of r4
+st08 r2, r4     // write byte to I/O device
+br always >loop // branch back to loop (BDS!)
+clr r1          // reset counter
+
+nop
+nop

programs/test2.prog

@@ -0,0 +1,50 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+irq3: br >irq_handler
+nop
+
+main: // actual start of program
+ldr sp, >sp_init
+
+ldr r1, >startvalue
+clr r2
+clr sr
+
+test: mov r1, pc
+
+loop: addi r2, 1
+cmp ll r2, r1
+br true >loop
+nop
+
+cmp le r2, r1
+
+call true >final
+addi r3, 1
+
+end: br >end
+nop
+
+final: addi r10, 1
+cmp eq r10, r1
+ret true
+nop
+br >final
+nop
+
+irq_handler: addi r4, 1
+reti
+
+
+nop
+nop
+nop
+nop
+.align
+sp_init: .word 1020
+startvalue: .word 15
+

programs/test_endianess.prog

@@ -0,0 +1,44 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+
+main: // actual start of program
+ldr sp, >sp_init
+
+clr r5
+clr r6
+clr r7
+clr r8
+clr r9
+
+ldr r0, >addr
+addi r1, 0x01
+st08 r0, r1
+ld08 r5, r0
+
+addi r0, 1
+addi r1, 1
+st08 r0, r1
+ld08 r6, r0
+
+addi r0, 1
+addi r1, 1
+st08 r0, r1
+ld08 r7, r0
+
+addi r0, 1
+addi r1, 1
+st08 r0, r1
+ld08 r8, r0
+
+addi r0, 1
+addi r1, 1
+st08 r0, r1
+ld08 r9, r0
+.align
+sp_init: .word 1020 // 0x3FC
+addr: .word 0x101
+

programs/test_endianess2.prog

@@ -0,0 +1,45 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+
+main: // actual start of program
+ldr sp, >sp_init
+
+clr r5
+clr r6
+clr r7
+clr r8
+clr r9
+
+ldr r0, >addr
+addi r1, 0x01
+st32 r0, r1
+ld32 r5, r0
+
+addi r0, 1
+addi r1, 1
+st32 r0, r1
+ld32 r6, r0
+
+addi r0, 1
+addi r1, 1
+st32 r0, r1
+ld32 r7, r0
+
+addi r0, 1
+addi r1, 1
+st32 r0, r1
+ld32 r8, r0
+
+addi r0, 1
+addi r1, 1
+st32 r0, r1
+ld32 r9, r0
+
+.align
+sp_init: .word 1020 // 0x3FC
+addr: .word 0x101
+

programs/test_sync.prog

@@ -0,0 +1,52 @@
+reset: br >main
+nop
+hardfault: reti
+nop
+memfault: reti
+nop
+
+.align
+sp_init:	.word 0x400 // Stackpointer Initial Value
+
+main:
+	ldr sp, >sp_init
+	clr sr
+
+//base addr
+add r0,r0,sp
+//addi r0,0x40
+addi r10,4
+add r1,r0,r10
+add r2,r1,r10
+
+//values t.b. stored
+addi r3,-1
+addi r4,-2
+addi r5,-3
+
+//store values
+st32 r0,r3
+st32 r1,r4
+st32 r2,r5
+
+//retrieve values
+
+ld32 r6,r0
+ld32 r7,r1
+ld32 r8,r2
+nop
+nop
+nop
+nop
+
+ld32 r6,r0
+st32 r1,r6
+ld32 r7,r0
+ld32 r7,r0
+st32 r1,r6
+st32 r1,r6
+ld32 r7,r0
+
+end:
+br always >end
+nop