Make switches module ready for real board

soc/peripheral/switches.vhd

@@ -38,8 +38,10 @@ begin
 				data	<= (others=>'0');
 			else
 				if wslvi.stb = '1' and wslvi.cyc = '1' then
-                    data(15 downto 0) <= switches;
-                    data(20 downto 16) <= buttons;
+				    if wslvi.we='0' then
+                        data(15 downto 0) <= switches;
+                        data(20 downto 16) <= buttons;
+                    end if;
 				
 					if ack = '0' then
 						ack	<= '1';

soc/testbench/switches_tb.vhd

@@ -57,15 +57,25 @@ BEGIN
 		switches <= "1001000101010111";
 		wait for CLK_PERIOD;
 		
-        data	<= (others => '0');
 		generate_sync_wb_single_read(slvi,slvo,clk,data);
 		
 		wait for 2 ns;
 		
-		data	<= (others => '0');
 		generate_sync_wb_single_read(slvi,slvo,clk,data);
+		
+		buttons <= "11011";
+		switches <= x"DEAD";
+        wait for 10 ns;
+		
+		generate_sync_wb_single_read(slvi,slvo,clk,data, SIZE => "00"); -- Single byte
+		
+        wait for 10 ns;
+		
+		generate_sync_wb_single_read(slvi,slvo,clk,data, SIZE => "01"); -- Half word
+		
+		wait for 100 ns;
 
-		wait;
+		assert false report "Simulation terminated!" severity failure;
 	end process stimuli;
 
 END ARCHITECTURE;