Add scrolling program

This commit is contained in:
2022-11-20 17:48:42 +01:00
parent 6a76243fc0
commit 4666ae9bf8
5 changed files with 414 additions and 16 deletions

View File

@@ -29,7 +29,7 @@ package config is
constant CFG_LED : integer := CFG_DMEM+1;
constant CFG_SW : integer := CFG_LED+1;
constant CFG_TIMER : integer := CFG_SW+1;
constant CFG_SEG : integer := CFG_TIMER+1;
constant CFG_SCR : integer := CFG_TIMER+1;
-----------------------------
-- base address (BADR) & mask address (MADR)

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@@ -52,6 +52,7 @@ begin
end if;
elsif buffer_clear = '1' then
ptr_last <= -1;
ptr_write <= 0;
end if;
end if;
end if;
@@ -65,17 +66,21 @@ begin
hex_char <= (others => '0');
else
hex_char <= (others => '0');
if next_char = '1' then
if ptr_last = -1 then -- Special case
hex_char <= (others => '0');
else
hex_char <= ring_buffer(ptr_read);
if ptr_read = ptr_last then
ptr_read <= 0;
if buffer_clear = '1' then
ptr_read <= 0;
else
if next_char = '1' then
if ptr_last = -1 then -- Special case
hex_char <= (others => '0');
else
ptr_read <= ptr_read + 1;
hex_char <= ring_buffer(ptr_read);
if ptr_read = ptr_last then
ptr_read <= 0;
else
ptr_read <= ptr_read + 1;
end if;
end if;
end if;
end if;

65
soc/testbench/warmup4.vhd Normal file
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@@ -0,0 +1,65 @@
-- See the file "LICENSE" for the full license governing this code. --
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY warmup4_tb IS
END ENTITY;
ARCHITECTURE sim OF warmup4_tb IS
constant CLK_PERIOD : time := 10 ns;
signal clk : std_logic := '0';
signal rst : std_logic;
signal led : std_logic_vector(7 downto 0);
signal btn : std_logic_vector(4 downto 0) := (others => '0');
signal sw : std_logic_vector(15 downto 0) := (others => '0');
signal anodes : std_logic_vector(7 downto 0);
signal cathodes : std_logic_vector(7 downto 0);
COMPONENT lt16soc_top IS
generic(
programfilename : string := "../../programs/scrolling.ram"
);
port(
clk : in std_logic;
rst : in std_logic;
led : out std_logic_vector(7 downto 0);
btn : in std_logic_vector(4 downto 0);
sw : in std_logic_vector(15 downto 0);
anodes : out std_logic_vector(7 downto 0);
cathodes : out std_logic_vector(7 downto 0)
);
END COMPONENT;
BEGIN
dut: lt16soc_top port map(
clk=>clk,
rst=>rst,
led=>led,
btn=>btn,
sw=>sw,
anodes=>anodes,
cathodes=>cathodes
);
clk_gen: process
begin
clk <= not clk;
wait for CLK_PERIOD/2;
end process clk_gen;
stimuli: process
begin
rst <= '0';
wait for CLK_PERIOD;
rst <= '1';
wait for 2ms;
assert false report "Simulation terminated!" severity failure;
end process stimuli;
END ARCHITECTURE;

View File

@@ -204,16 +204,16 @@ begin
clk,rst_gen,slvi(CFG_TIMER),slvo(CFG_TIMER), irq_lines(3)
);
segmentdev : wb_segment_adv
scrollingdev : wb_scrolling
generic map(
memaddr => CFG_BADR_SEG,
addrmask => CFG_MADR_SEG
memaddr => CFG_BADR_SCR,
addrmask => CFG_MADR_SCR
)
port map(
clk => clk,
rst => rst_gen,
wslvi => slvi(CFG_SEG),
wslvo => slvo(CFG_SEG),
wslvi => slvi(CFG_SCR),
wslvo => slvo(CFG_SCR),
anodes => anodes,
cathodes => cathodes