Modify program to adapt for new register layout

2022-11-13 11:17:10 +01:00
parent ced12b01f0
commit 15f51c1793
2 changed files with 170 additions and 1 deletions
--- a/soc/testbench/warmup3.vhd
+++ b/soc/testbench/warmup3.vhd
@@ -21,7 +21,7 @@ ARCHITECTURE sim OF warmup3_tb IS

 	COMPONENT lt16soc_top IS
 		generic(
-			programfilename : string := "../../programs/segments_test.ram"
+			programfilename : string := "../../programs/segments_adv_test.ram"
 		);
 		port(
 			clk		: in  std_logic;