derek/lt16lab
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Integrate timer module in top and add test program

Browse Source
This commit is contained in:
Derek Christ
2022-11-06 17:45:31 +01:00
parent dd4ca39450
commit 1562d668a1
3 changed files with 124 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
soc/top/top.vhd
View File

@@ -37,7 +37,7 @@ architecture RTL of lt16soc_top is
signal rst_gen : std_logic;
constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_0000_0000_0001";
constant slv_mask_vector : std_logic_vector(0 to NWBSLV-1) := b"1111_1000_0000_0001";
constant mst_mask_vector : std_logic_vector(0 to NWBMST-1) := b"1000";
signal slvo : wb_slv_out_vector := (others=> wbs_out_none);
@@ -192,5 +192,13 @@ begin
port map(
clk,rst_gen,slvi(CFG_SW),slvo(CFG_SW), btn, sw
);
timerdev : wb_timer
generic map(
CFG_BADR_TIMER,CFG_MADR_TIMER
)
port map(
clk,rst_gen,slvi(CFG_TIMER),slvo(CFG_TIMER), irq_lines(3)
);
end architecture RTL;