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The ISA parser now emits the code required to access matrix registers. In the case where a register is both a source and a destination, the ISA parser generates appropriate code to make sure that the contents of the source is copied to the destination. This is required for the O3 CPU which treats these as two different physical registers, and hence data is lost if not explicitly preserved. Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289 Change-Id: I8796bd1ea55b5edf5fb8ab92ef1a6060ccc58fa1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64338 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>