Curtis Dunham fc8fd0fd18 arm: bank GIC registers per CPU ...

Updated according to GICv2 documentation.

Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

2016-08-02 13:35:45 +01:00

..

alpha

style: fix missing spaces in control statements

2016-02-06 17:21:19 -08:00

arm

arm: bank GIC registers per CPU

2016-08-02 13:35:45 +01:00

i2c

dev: Add missing SConscript in src/dev/i2c

2015-12-10 18:46:02 +00:00

mips

scons: Add missing override to appease clang

2016-02-23 03:27:20 -05:00

net

dev, dist: Fixed a scheduling bug in the etherswitch

2016-07-19 09:48:56 -05:00

pci

sim: Call regStats of base-class as well

2016-06-06 17:16:43 +01:00

sparc

scons: Add missing override to appease clang

2016-02-23 03:27:20 -05:00

storage

sim: Call regStats of base-class as well

2016-06-06 17:16:43 +01:00

virtio

dev, virtio: properly set PCI address space to use IOREG

2016-05-19 15:19:34 -05:00

x86

misc: Add missing overrides to appease clang

2016-02-15 03:40:32 -05:00

baddev.cc

dev: Include basic devices in NULL ISA build

2014-02-18 05:50:59 -05:00

baddev.hh

AddrRange: Transition from Range<T> to AddrRange

2012-09-19 06:15:44 -04:00

BadDevice.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

Device.py

dev: Fix IsaFake's cxx_header setting

2014-03-23 11:11:37 -04:00

dma_device.cc

mem: Make cache terminology easier to understand

2015-12-31 09:32:58 -05:00

dma_device.hh

misc: Add explicit overrides and fix other clang >= 3.5 issues

2015-10-12 04:08:01 -04:00

intel_8254_timer.cc

style: fix missing spaces in control statements

2016-02-06 17:21:19 -08:00

intel_8254_timer.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

io_device.cc

mem: Use the packet delays and do not just zero them out

2015-11-06 03:26:36 -05:00

io_device.hh

sim: Decouple draining from the SimObject hierarchy

2015-07-07 09:51:05 +01:00

isa_fake.cc

mem: Remove redundant Packet::allocate calls

2014-12-02 06:07:41 -05:00

isa_fake.hh

AddrRange: Transition from Range<T> to AddrRange

2012-09-19 06:15:44 -04:00

mc146818.cc

style: remove trailing whitespace

2016-02-06 17:21:18 -08:00

mc146818.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

pixelpump.cc

dev: Implement a simple display timing generator

2015-08-07 09:59:26 +01:00

pixelpump.hh

misc: Remove redundant compiler-specific defines

2015-10-12 04:07:59 -04:00

platform.cc

dev: Rewrite PCI host functionality

2015-12-05 00:11:24 +00:00

platform.hh

dev: Rewrite PCI host functionality

2015-12-05 00:11:24 +00:00

Platform.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

ps2.cc

dev: Support translating left and right ALT keys.

2014-12-03 03:06:03 -08:00

ps2.hh

ARM: PS2 encoding fix

2012-06-05 01:23:10 -04:00

rtcreg.h

dev: Clean up MC146818 register (A & B) handling

2013-06-03 12:28:41 +02:00

SConscript

dev: Move storage devices to src/dev/storage/

2015-12-10 10:35:23 +00:00

terminal.cc

dev: Fix incorrect terminal backlog handling

2016-04-27 15:33:58 +01:00

terminal.hh

base: Add support for changing output directories

2015-11-27 14:41:59 +00:00

Terminal.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

uart8250.cc

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

uart8250.hh

misc: Add explicit overrides and fix other clang >= 3.5 issues

2015-10-12 04:08:01 -04:00

uart.cc

dev: Refactor terminal<->UART interface to make it more generic

2014-09-20 17:17:50 -04:00

uart.hh

dev: Refactor terminal<->UART interface to make it more generic

2014-09-20 17:17:50 -04:00

Uart.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00