0cacf7e817
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles. In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
122 lines
3.7 KiB
C++
122 lines
3.7 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Steve Reinhardt
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*/
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#ifndef __ARCH_ALPHA_UTILITY_HH__
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#define __ARCH_ALPHA_UTILITY_HH__
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/registers.hh"
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#include "arch/alpha/types.hh"
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#include "base/misc.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/thread_context.hh"
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#include "arch/alpha/ev5.hh"
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namespace AlphaISA {
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inline PCState
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buildRetPC(const PCState &curPC, const PCState &callPC)
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{
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PCState retPC = callPC;
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retPC.advance();
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return retPC;
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}
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uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
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inline bool
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inUserMode(ThreadContext *tc)
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{
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return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
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}
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param tc The thread context.
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*/
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template <class TC>
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void zeroRegisters(TC *tc);
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// Alpha IPR register accessors
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inline bool PcPAL(Addr addr) { return addr & 0x3; }
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inline void startupCPU(ThreadContext *tc, int cpuId)
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{ tc->activate(Cycles(0)); }
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////////////////////////////////////////////////////////////////////////
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//
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// Translation stuff
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//
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inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
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// User Virtual
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inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
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// Kernel Direct Mapped
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inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
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inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
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// Kernel Virtual
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inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
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inline Addr
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TruncPage(Addr addr)
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{ return addr & ~(PageBytes - 1); }
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inline Addr
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RoundPage(Addr addr)
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{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
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void initIPRs(ThreadContext *tc, int cpuId);
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void initCPU(ThreadContext *tc, int cpuId);
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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void skipFunction(ThreadContext *tc);
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inline void
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advancePC(PCState &pc, const StaticInstPtr inst)
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{
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pc.advance();
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}
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inline uint64_t
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getExecutingAsid(ThreadContext *tc)
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{
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return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
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}
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} // namespace AlphaISA
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#endif // __ARCH_ALPHA_UTILITY_HH__
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