Andreas Sandberg fb52ea9220 arm: Invalidate cached TLB configuration in drainResume ...

Currently, we invalidate the cached miscregs in
TLB::unserialize(). The intended use of the drainResume() method is to
invalidate cached state and prepare the system to resume after a CPU
handover or (un)serialization. This patch moves the TLB miscregs
invalidation code to the drainResume() method to avoid surprising
behavior.

2013-01-07 13:05:45 -05:00

..

alpha

arch: Move the ISA object to a separate section

2013-01-07 13:05:42 -05:00

arm

arm: Invalidate cached TLB configuration in drainResume

2013-01-07 13:05:45 -05:00

generic

arch: Fix broken M5VarArgsFault initialization

2013-01-07 13:05:38 -05:00

mips

arch: Move the ISA object to a separate section

2013-01-07 13:05:42 -05:00

noisa

cpu: add separate stats for insts/ops both globally and per cpu model

2012-02-12 16:07:39 -06:00

power

arch: Move the ISA object to a separate section

2013-01-07 13:05:42 -05:00

sparc

arch: Move the ISA object to a separate section

2013-01-07 13:05:42 -05:00

x86

arch: Move the ISA object to a separate section

2013-01-07 13:05:42 -05:00

isa_parser.py

O3: Clean up the O3 structures and try to pack them a bit better.

2012-06-05 01:23:09 -04:00

micro_asm_test.py

Add a second section to make sure the ROM is extended properly.

2007-05-31 22:21:21 +00:00

micro_asm.py

scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access

2009-09-22 15:24:16 -07:00

SConscript

CPU: Merge the predecoder and decoder.

2012-05-26 13:44:46 -07:00