1daf4bf39d
Despite the generic sounding name and sort of generic contents, the BaseDynInst was actually tied to the O3 CPU. Having the two independent moving pieces created complexity but provided no real benefit. This was evidenced by the fact that no CPU other than O3 actually used that class. Change-Id: I4ea1d053e2e172ececdc3113b8d76d5ad7490fc7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42094 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
77 lines
2.7 KiB
Python
Executable File
77 lines
2.7 KiB
Python
Executable File
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import sys
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Import('*')
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if 'O3CPU' in env['CPU_MODELS']:
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SimObject('FUPool.py')
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SimObject('FuncUnitConfig.py')
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SimObject('O3CPU.py')
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Source('commit.cc')
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Source('cpu.cc')
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Source('decode.cc')
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Source('dyn_inst.cc')
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Source('fetch.cc')
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Source('free_list.cc')
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Source('fu_pool.cc')
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Source('iew.cc')
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Source('inst_queue.cc')
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Source('lsq.cc')
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Source('lsq_unit.cc')
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Source('mem_dep_unit.cc')
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Source('regfile.cc')
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Source('rename.cc')
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Source('rename_map.cc')
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Source('rob.cc')
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Source('scoreboard.cc')
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Source('store_set.cc')
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Source('thread_context.cc')
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DebugFlag('CommitRate')
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DebugFlag('IEW')
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DebugFlag('IQ')
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DebugFlag('LSQ')
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DebugFlag('LSQUnit')
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DebugFlag('MemDepUnit')
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DebugFlag('O3CPU')
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DebugFlag('ROB')
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DebugFlag('Rename')
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DebugFlag('Scoreboard')
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DebugFlag('StoreSet')
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DebugFlag('Writeback')
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CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
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'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
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'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
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SimObject('O3Checker.py')
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Source('checker.cc')
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