Giacomo Travaglini f7d6dadc10 mem-ruby: Allow trivial integer operations with Addr type ...

At the moment an address value can only be used in the slicc code
to do TBE lookups but there is no way to add/subtract/divide/multiply
two addresses nor an address and an integer value.

This hinders the development of protocol specific code and
forces developers to place such code in shared
C++ structures

Change-Id: Ia184e793b6cd38f951f475a7cdf284f529972ccb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

2023-09-08 08:38:13 +01:00

..

arch

arch-x86: Fix wrong x86 assembly

2023-09-01 00:26:51 +00:00

base

base: Make 'findLsbSetFallback' constexpr to fix gcc-8 comp

2023-08-21 14:04:36 -07:00

cpu

cpu-minor: Separate the reg_index of VecClassReg and VecElemReg

2023-08-24 13:27:27 +08:00

dev

gpu-compute: Use timing DMAs for GPUFS HSA signals

2023-08-25 13:10:51 -05:00

doc

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doxygen

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gpu-compute

gpu-compute: Set LDS/scratch aperture base register

2023-08-31 11:01:32 -05:00

kern

misc: Fix buggy special path comparisons

2023-09-05 13:44:10 -07:00

learning_gem5

learning-gem5: Add a missing override

2023-07-26 20:01:37 -07:00

mem

mem-ruby: Allow trivial integer operations with Addr type

2023-09-08 08:38:13 +01:00

proto

scons: Use pkgconfig to get correct Protobuf dependency (#68)

2023-07-17 15:29:05 -07:00

python

resources,stdlib: Add workload to resource specialization and deprecate workload.py (#212)

2023-09-07 12:45:45 -07:00

sim

sim: add bypass_on_change to the set() of a signal

2023-09-07 11:54:56 +08:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

misc: Use python f-strings for string formatting

2023-03-16 09:05:29 +00:00

Doxyfile

misc: Update version info for develop branch

2023-07-10 12:28:44 -07:00

SConscript

scons: Add extra parent dir to CPPPATH if --no-duplicate-sources (#104)

2023-07-20 09:35:45 -07:00