Giacomo Travaglini 330a5f7bad misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB ...

With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-10-21 09:33:39 +00:00

..

msi_caches.py

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

2020-10-21 09:33:39 +00:00

ruby_caches_MI_example.py

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

2020-10-21 09:33:39 +00:00

ruby_test.py

config: Delete authors lists from config files.

2020-02-17 10:06:07 +00:00

simple_ruby.py

configs,tests: Update configs to use compatible SE workloads.

2020-10-13 04:59:04 +00:00

test_caches.py

mem-ruby: Sequencer can be used without cache

2020-10-12 14:09:55 +00:00