ec91492feb
Change-Id: If8c2e08779f4be59112fe130ab651dfce7065111 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49303 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
49 lines
2.3 KiB
Python
49 lines
2.3 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from ..abstract_dma_controller import AbstractDMAController
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from .....utils.override import overrides
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from m5.objects import MessageBuffer
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class DMAController(AbstractDMAController):
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"""
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A DMA Controller for use in the MI_Example cache hierarchy setup.
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"""
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class DMAController(AbstractDMAController):
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def __init__(self, network, cache_line_size):
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super(DMAController, self).__init__(network, cache_line_size)
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@overrides(AbstractDMAController)
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def connectQueues(self, network):
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self.mandatoryQueue = MessageBuffer()
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self.requestToDir = MessageBuffer()
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self.requestToDir.out_port = network.in_port
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self.responseFromDir = MessageBuffer(ordered=True)
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self.responseFromDir.in_port = network.out_port
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