python: Add MI_Example cache hierarchy to the components lib
Change-Id: If8c2e08779f4be59112fe130ab651dfce7065111 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49303 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
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# Copyright (c) 2021 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from ..abstract_directory import AbstractDirectory
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from .....utils.override import overrides
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from m5.objects import (
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MessageBuffer,
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RubyDirectoryMemory,
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)
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class Directory(AbstractDirectory):
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"""
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The directory controller for the MI_Example cache hierarchy.
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"""
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def __init__(self, network, cache_line_size, mem_range, port):
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super(Directory, self).__init__(network, cache_line_size)
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self.addr_ranges = [mem_range]
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self.directory = RubyDirectoryMemory()
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# Connect this directory to the memory side.
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self.memory_out_port = port
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@overrides(AbstractDirectory)
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def connectQueues(self, network):
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self.requestToDir = MessageBuffer(ordered=True)
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self.requestToDir.in_port = network.out_port
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self.dmaRequestToDir = MessageBuffer(ordered=True)
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self.dmaRequestToDir.in_port = network.out_port
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self.responseFromDir = MessageBuffer()
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self.responseFromDir.out_port = network.in_port
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self.dmaResponseFromDir = MessageBuffer(ordered=True)
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self.dmaResponseFromDir.out_port = network.in_port
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self.forwardFromDir = MessageBuffer()
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self.forwardFromDir.out_port = network.in_port
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self.requestToMemory = MessageBuffer()
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self.responseFromMemory = MessageBuffer()
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@@ -0,0 +1,48 @@
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# Copyright (c) 2021 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from ..abstract_dma_controller import AbstractDMAController
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from .....utils.override import overrides
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from m5.objects import MessageBuffer
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class DMAController(AbstractDMAController):
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"""
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A DMA Controller for use in the MI_Example cache hierarchy setup.
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"""
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class DMAController(AbstractDMAController):
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def __init__(self, network, cache_line_size):
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super(DMAController, self).__init__(network, cache_line_size)
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@overrides(AbstractDMAController)
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def connectQueues(self, network):
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self.mandatoryQueue = MessageBuffer()
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self.requestToDir = MessageBuffer()
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self.requestToDir.out_port = network.in_port
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self.responseFromDir = MessageBuffer(ordered=True)
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self.responseFromDir.in_port = network.out_port
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@@ -0,0 +1,69 @@
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# Copyright (c) 2021 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from .....utils.override import overrides
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from .....processors.abstract_core import AbstractCore
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from .....isas import ISA
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from ..abstract_l1_cache import AbstractL1Cache
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from m5.objects import (
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MessageBuffer,
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RubyCache,
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ClockDomain,
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)
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class L1Cache(AbstractL1Cache):
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def __init__(
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self,
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size: str,
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assoc: int,
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network,
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core: AbstractCore,
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cache_line_size,
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target_isa: ISA,
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clk_domain: ClockDomain,
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):
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super(L1Cache, self).__init__(network, cache_line_size)
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self.cacheMemory = RubyCache(
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size=size, assoc=assoc, start_index_bit=self.getBlockSizeBits()
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)
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self.clk_domain = clk_domain
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self.send_evictions = self.sendEvicts(core=core, target_isa=target_isa)
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@overrides(AbstractL1Cache)
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def connectQueues(self, network):
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self.mandatoryQueue = MessageBuffer()
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self.requestFromCache = MessageBuffer(ordered=True)
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self.requestFromCache.out_port = network.in_port
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self.responseFromCache = MessageBuffer(ordered=True)
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self.responseFromCache.out_port = network.in_port
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self.forwardToCache = MessageBuffer(ordered=True)
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self.forwardToCache.in_port = network.out_port
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self.responseToCache = MessageBuffer(ordered=True)
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self.responseToCache.in_port = network.out_port
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@@ -0,0 +1,186 @@
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# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from .caches.mi_example.l1_cache import L1Cache
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from .caches.mi_example.dma_controller import DMAController
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from .caches.mi_example.directory import Directory
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from .topologies.simple_pt2pt import SimplePt2Pt
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from .abstract_ruby_cache_hierarhcy import AbstractRubyCacheHierarchy
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from ..abstract_cache_hierarchy import AbstractCacheHierarchy
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from ...boards.abstract_board import AbstractBoard
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from ...coherence_protocol import CoherenceProtocol
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from ...isas import ISA
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from ...utils.override import overrides
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from ...runtime import get_runtime_coherence_protocol, get_runtime_isa
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from m5.objects import (
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RubySystem,
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RubySequencer,
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DMASequencer,
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RubyPortProxy,
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)
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class MIExampleCacheHierarchy(AbstractRubyCacheHierarchy):
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"""
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The MI_Example cache hierarchy creates a Ruby cache for each code in a
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simple point-to-point topology.
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"""
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def __init__(
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self,
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size: str,
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assoc: str,
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):
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"""
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:param size: The size of each cache in the heirarchy.
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:param assoc: The associativity of each cache.
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"""
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super().__init__()
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self._size = size
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self._assoc = assoc
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@overrides(AbstractCacheHierarchy)
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def incorporate_cache(self, board: AbstractBoard) -> None:
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if get_runtime_coherence_protocol() != CoherenceProtocol.MI_EXAMPLE:
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raise EnvironmentError(
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"The MIExampleCacheHierarchy must be used with with the "
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"MI_EXAMPLE coherence protocol."
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)
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self.ruby_system = RubySystem()
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# Ruby's global network.
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self.ruby_system.network = SimplePt2Pt(self.ruby_system)
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# MI Example users 5 virtual networks.
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self.ruby_system.number_of_virtual_networks = 5
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self.ruby_system.network.number_of_virtual_networks = 5
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# There is a single global list of all of the controllers to make it
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# easier to connect everything to the global network. This can be
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# customized depending on the topology/network requirements.
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# Create one controller for each L1 cache (and the cache mem obj.)
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# Create a single directory controller (Really the memory cntrl).
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self._controllers = []
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for i, core in enumerate(board.get_processor().get_cores()):
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cache = L1Cache(
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size=self._size,
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assoc=self._assoc,
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network=self.ruby_system.network,
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core=core,
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cache_line_size=board.get_cache_line_size(),
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target_isa=get_runtime_isa(),
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clk_domain=board.get_clock_domain(),
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)
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if board.has_io_bus():
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cache.sequencer = RubySequencer(
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version=i,
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dcache=cache.cacheMemory,
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clk_domain=cache.clk_domain,
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pio_request_port=board.get_io_bus().cpu_side_ports,
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mem_request_port=board.get_io_bus().cpu_side_ports,
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pio_response_port=board.get_io_bus().mem_side_ports,
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)
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else:
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cache.sequencer = RubySequencer(
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version=i,
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dcache=cache.L1Dcache,
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clk_domain=cache.clk_domain,
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)
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cache.ruby_system = self.ruby_system
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core.connect_icache(cache.sequencer.in_ports)
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core.connect_dcache(cache.sequencer.in_ports)
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core.connect_walker_ports(
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cache.sequencer.in_ports, cache.sequencer.in_ports
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)
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# Connect the interrupt ports
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if get_runtime_isa() == ISA.X86:
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int_req_port = cache.sequencer.interrupt_out_port
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int_resp_port = cache.sequencer.in_ports
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core.connect_interrupt(int_req_port, int_resp_port)
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else:
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core.connect_interrupt()
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cache.ruby_system = self.ruby_system
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self._controllers.append(cache)
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# Create the directory controllers
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self._directory_controllers = []
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for range, port in board.get_memory().get_mem_ports():
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dir = Directory(
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self.ruby_system.network,
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board.get_cache_line_size(),
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range,
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port,
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)
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dir.ruby_system = self.ruby_system
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self._directory_controllers.append(dir)
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# Create the DMA Controllers, if required.
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self._dma_controllers = []
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if board.has_dma_ports():
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dma_ports = board.get_dma_ports()
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for i, port in enumerate(dma_ports):
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ctrl = DMAController(
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self.ruby_system.network, board.get_cache_line_size()
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)
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ctrl.dma_sequencer = DMASequencer(version=i, in_ports=port)
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ctrl.ruby_system = self.ruby_system
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ctrl.dma_sequencer.ruby_system = self.ruby_system
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self._dma_controllers.append(ctrl)
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self.ruby_system.num_of_sequencers = len(self._controllers) + len(
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self._dma_controllers
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)
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# Connect the controllers.
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self.ruby_system.controllers = self._controllers
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self.ruby_system.directory_controllers = self._directory_controllers
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if len(self._dma_controllers) != 0:
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self.ruby_system.dma_controllers = self._dma_controllers
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self.ruby_system.network.connectControllers(
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self._controllers
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+ self._directory_controllers
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+ self._dma_controllers
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)
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self.ruby_system.network.setup_buffers()
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# Set up a proxy port for the system_port. Used for load binaries and
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# other functional-only things.
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self.ruby_system.sys_port_proxy = RubyPortProxy()
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board.connect_system_port(self.ruby_system.sys_port_proxy.in_ports)
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