e73655d038
This patch has been generated by applying flynt to the gem5 repo (ext has been excluded) JIRA: https://gem5.atlassian.net/browse/GEM5-831 Change-Id: I0935db6223d5426b99515959bde78e374cbadb04 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68957 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
98 lines
3.7 KiB
Python
98 lines
3.7 KiB
Python
# Copyright (c) 2020 ARM Limited
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2018 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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Test file containing simple workloads to run on CPU models.
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Each test takes ~10 seconds to run.
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"""
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from testlib import *
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workloads = ("Bubblesort", "FloatMM")
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valid_isas = {
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constants.vega_x86_tag: (
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"X86AtomicSimpleCPU",
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"X86TimingSimpleCPU",
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"X86DerivO3CPU",
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),
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constants.arm_tag: (
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"ArmAtomicSimpleCPU",
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"ArmTimingSimpleCPU",
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"ArmMinorCPU",
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"ArmDerivO3CPU",
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),
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constants.riscv_tag: (
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"RiscvAtomicSimpleCPU",
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"RiscvTimingSimpleCPU",
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"RiscvMinorCPU",
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"RiscvDerivO3CPU",
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),
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}
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base_path = joinpath(config.bin_path, "cpu_tests")
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base_url = config.resource_url + "/test-progs/cpu-tests/bin/"
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isa_url = {
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constants.vega_x86_tag: base_url + "x86",
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constants.arm_tag: base_url + "arm",
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constants.riscv_tag: base_url + "riscv",
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}
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for isa in valid_isas:
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path = joinpath(base_path, isa.lower())
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for workload in workloads:
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ref_path = joinpath(getcwd(), "ref", workload)
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verifiers = (verifier.MatchStdout(ref_path),)
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url = isa_url[isa] + "/" + workload
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workload_binary = DownloadedProgram(url, path, workload)
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binary = joinpath(workload_binary.path, workload)
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for cpu in valid_isas[isa]:
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gem5_verify_config(
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name=f"cpu_test_{cpu}_{workload}",
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verifiers=verifiers,
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config=joinpath(getcwd(), "run.py"),
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config_args=[f"--cpu={cpu}", binary],
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valid_isas=(constants.all_compiled_tag,),
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fixtures=[workload_binary],
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)
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