59496b6136
The [[nodiscard]] attribute is now standard, so we can use that directly. Change-Id: I57f59935858facb2a15bf4712be4bfd584bf0c7e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48509 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
132 lines
4.8 KiB
C++
132 lines
4.8 KiB
C++
/*
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* Copyright (c) 2012-2018 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Specifies a non-coherent cache. The non-coherent cache is expected
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* to be located below the point of coherency. All valid blocks in the
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* non-coherent cache can always be written to without any prior
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* invalidations or snoops.
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*/
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#ifndef __MEM_CACHE_NONCOHERENT_CACHE_HH__
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#define __MEM_CACHE_NONCOHERENT_CACHE_HH__
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#include "base/compiler.hh"
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#include "base/logging.hh"
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#include "base/types.hh"
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#include "mem/cache/base.hh"
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#include "mem/packet.hh"
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namespace gem5
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{
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class CacheBlk;
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class MSHR;
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struct NoncoherentCacheParams;
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/**
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* A non-coherent cache
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*/
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class NoncoherentCache : public BaseCache
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{
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protected:
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bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
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PacketList &writebacks) override;
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void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
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Tick forward_time,
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Tick request_time) override;
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void recvTimingReq(PacketPtr pkt) override;
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void doWritebacks(PacketList& writebacks,
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Tick forward_time) override;
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void doWritebacksAtomic(PacketList& writebacks) override;
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void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
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CacheBlk *blk) override;
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void recvTimingResp(PacketPtr pkt) override;
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void recvTimingSnoopReq(PacketPtr pkt) override {
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panic("Unexpected timing snoop request %s", pkt->print());
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}
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void recvTimingSnoopResp(PacketPtr pkt) override {
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panic("Unexpected timing snoop response %s", pkt->print());
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}
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Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
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PacketList &writebacks) override;
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Tick recvAtomic(PacketPtr pkt) override;
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Tick recvAtomicSnoop(PacketPtr pkt) override {
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panic("Unexpected atomic snoop request %s", pkt->print());
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}
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void functionalAccess(PacketPtr pkt, bool from_cpu_side) override;
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void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
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bool deferred_response = false,
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bool pending_downgrade = false) override;
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/*
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* Creates a new packet with the request to be send to the memory
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* below. The noncoherent cache is below the point of coherence
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* and therefore all fills bring in writable, therefore the
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* needs_writeble parameter is ignored.
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*/
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PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
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bool needs_writable,
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bool is_whole_line_write) const override;
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[[nodiscard]] PacketPtr evictBlock(CacheBlk *blk) override;
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public:
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NoncoherentCache(const NoncoherentCacheParams &p);
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};
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} // namespace gem5
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#endif // __MEM_CACHE_NONCOHERENTCACHE_HH__
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