Alec Roelke 7352324d4d arch-riscv: Fix compressed branch op offset ...

There is a bug in RISC-V's compressed branch instructions where the
offsets are not stored in ImmOp's immediate field, causing incorrect
branchTarget() return values.  This patch adds a new compressed branch
op format, CBOp, which correctly stores the offset.

Change-Id: Iac6e9b091d63f3dce4717ee5a9ec31a7cbd6c377
Reviewed-on: https://gem5-review.googlesource.com/8441
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

2018-02-19 20:31:33 +00:00

..

insts

riscv: Add overrides to various StaticInst methods.

2018-01-29 23:49:36 +00:00

isa

arch-riscv: Fix compressed branch op offset

2018-02-19 20:31:33 +00:00

linux

arch-riscv: Ignore sched_yield syscall in SE mode

2018-01-05 15:34:20 +00:00

decoder.cc

riscv,x86: Stop using the arch Nop machine instruction unnecessarily.

2017-12-23 03:36:45 +00:00

decoder.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

faults.cc

riscv: Fix bugs with RISC-V decoder and detailed CPUs

2017-07-14 20:29:25 +00:00

faults.hh

riscv: Fix bugs with RISC-V decoder and detailed CPUs

2017-07-14 20:29:25 +00:00

idle_event.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

idle_event.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

interrupts.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

interrupts.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

isa_traits.hh

alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.

2018-01-10 12:19:54 +00:00

isa.cc

arch-riscv: Restructure ISA description

2017-07-11 03:37:04 +00:00

isa.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

kernel_stats.hh

stats: Get rid of some kernel stats related cruft.

2017-09-11 04:58:38 +00:00

locked_mem.cc

riscv: fix Linux problems with LR and SC ops

2017-04-05 20:21:59 +00:00

locked_mem.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

microcode_rom.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

mmapped_ipr.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

pagetable.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

pagetable.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

pra_constants.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

process.cc

arch, mem, sim: Consolidate and rename the SE mode page table classes.

2018-01-19 20:20:57 +00:00

process.hh

arch,mem: Move page table construction into the arch classes.

2018-01-11 06:29:58 +00:00

pseudo_inst.hh

misc: Rename misc.(hh|cc) to logging.(hh|cc)

2017-12-04 23:10:55 +00:00

registers.hh

arch-riscv: Correct syscall argument reg count

2018-01-05 04:46:25 +00:00

remote_gdb.cc

arch, mem: Make the page table lookup function return a pointer.

2018-01-20 08:06:56 +00:00

remote_gdb.hh

sim, arch, base: Refactor the base remote GDB class.

2018-01-20 07:28:42 +00:00

RiscvInterrupts.py

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

RiscvISA.py

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

RiscvSystem.py

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

RiscvTLB.py

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

SConscript

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

SConsopts

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

stacktrace.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

stacktrace.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

system.cc

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

system.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00

tlb.cc

arch,cpu: "virtualize" the TLB interface.

2017-12-22 23:16:03 +00:00

tlb.hh

arch,cpu: "virtualize" the TLB interface.

2017-12-22 23:16:03 +00:00

types.hh

arch-riscv: Add support for compressed extension RV64C

2017-07-11 03:45:14 +00:00

utility.hh

riscv: Fix bugs with RISC-V decoder and detailed CPUs

2017-07-14 20:29:25 +00:00

vtophys.hh

arch: [Patch 1/5] Added RISC-V base instruction set RV64I

2016-11-30 17:10:28 -05:00