Adrian Herrera d266a37e5e misc: pass ThreadContext on ISA clear ...

This patch changes the clear API for the ISAs to pass the ThreadContext
issuing the call. This allows the ISA to carry out maintainance
operations on the TC state.

Change-Id: I40d6cf39c321521a221146aa0fd8f2cf665d39c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25465
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-02-19 17:32:46 +00:00

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bare_metal

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insts

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isa

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linux

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decoder.cc

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faults.cc

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isa_traits.hh

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isa.cc

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isa.hh

misc: pass ThreadContext on ISA clear

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kernel_stats.hh

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locked_mem.cc

riscv: fix AMO, LR and SC instructions

2019-02-08 15:27:04 +00:00

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RiscvInterrupts.py

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RiscvISA.py

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RiscvSystem.py

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RiscvTLB.py

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SConscript

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