de7337a32a
In order to fix several regression failures [1] the master/slave terminology in src/cpu/BaseCPU.py was reintroduced [2]. This patch is addressing the issue by providing 2 different ways of connecting cpu ports: *) connectBus: The method assumes an object with a bus interface is passed as an argument, therefore it tries to bind cpu ports to the bus.mem_side_ports and bus.cpu_side_ports *) connectAllPorts: No assumption on the port owning device is made. The method simply accepts ports as arguments which will be directly connected to the peer cpu ports This will be used for example by ruby Sequencers [1]: https://gem5.atlassian.net/browse/GEM5-775 [2]: https://gem5-review.googlesource.com/c/public/gem5/+/34495 Change-Id: I715ab8471621d6e5eb36731d7eaefbedf9663a71 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52584 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
141 lines
6.2 KiB
Python
141 lines
6.2 KiB
Python
# Copyright (c) 2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# Copyright (c) 2020 ARM Limited
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.ClockedObject import ClockedObject
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class RubyPort(ClockedObject):
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type = 'RubyPort'
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abstract = True
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cxx_header = "mem/ruby/system/RubyPort.hh"
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cxx_class = 'gem5::ruby::RubyPort'
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version = Param.Int(0, "")
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in_ports = VectorResponsePort("CPU side of this RubyPort/Sequencer. "
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"The CPU request ports should be connected to this. If a CPU "
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"has multiple ports (e.g., I/D ports) all of the ports for a "
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"single CPU can connect to one RubyPort.")
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slave = DeprecatedParam(in_ports, '`slave` is now called `in_ports`')
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interrupt_out_port = VectorRequestPort("Port to connect to x86 interrupt "
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"controller to send the CPU requests from outside.")
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master = DeprecatedParam(interrupt_out_port,
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'`master` is now called `interrupt_out_port`')
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pio_request_port = RequestPort("Ruby pio request port")
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pio_master_port = DeprecatedParam(pio_request_port,
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'`pio_master_port` is now called `pio_request_port`')
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mem_request_port = RequestPort("Ruby mem request port")
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mem_master_port = DeprecatedParam(mem_request_port,
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'`mem_master_port` is now called `mem_request_port`')
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pio_response_port = ResponsePort("Ruby pio response port")
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pio_slave_port = DeprecatedParam(pio_response_port,
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'`pio_slave_port` is now called `pio_response_port`')
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using_ruby_tester = Param.Bool(False, "")
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no_retry_on_stall = Param.Bool(False, "")
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ruby_system = Param.RubySystem(Parent.any, "")
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system = Param.System(Parent.any, "system object")
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support_data_reqs = Param.Bool(True, "data cache requests supported")
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support_inst_reqs = Param.Bool(True, "inst cache requests supported")
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is_cpu_sequencer = Param.Bool(True, "connected to a cpu")
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class RubyPortProxy(RubyPort):
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type = 'RubyPortProxy'
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cxx_header = "mem/ruby/system/RubyPortProxy.hh"
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cxx_class = 'gem5::ruby::RubyPortProxy'
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class RubySequencer(RubyPort):
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type = 'RubySequencer'
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cxx_class = 'gem5::ruby::Sequencer'
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cxx_header = "mem/ruby/system/Sequencer.hh"
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dcache = Param.RubyCache("")
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max_outstanding_requests = Param.Int(16,
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"max requests (incl. prefetches) outstanding")
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deadlock_threshold = Param.Cycles(500000,
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"max outstanding cycles for a request "
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"before deadlock/livelock declared")
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garnet_standalone = Param.Bool(False, "")
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# id used by protocols that support multiple sequencers per controller
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# 99 is the dummy default value
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coreid = Param.Int(99, "CorePair core id")
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def connectCpuPorts(self, cpu):
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"""
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Helper for connecting all cpu memory request output ports to this
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object's in_ports.
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This assumes the provided cpu object is an instance of BaseCPU. Non-cpu
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objects should use connectInstPort and connectDataPort.
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"""
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import m5.objects
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assert(isinstance(cpu, m5.objects.BaseCPU))
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# this connects all cpu mem-side ports to self.in_ports
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cpu.connectAllPorts(
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self.in_ports, self.in_ports, self.interrupt_out_port)
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def connectIOPorts(self, piobus):
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"""
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Helper for connecting this object's IO request and response ports to
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the provided bus object. Usually a iobus object is used to wireup IO
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components in a full system simulation. Incoming/Outgoing IO requests
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do not go though the SLICC protocol so the iobus must be connected to
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the sequencer directly.
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"""
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self.pio_request_port = piobus.cpu_side_ports
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self.mem_request_port = piobus.cpu_side_ports
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self.pio_response_port = piobus.mem_side_ports
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class RubyHTMSequencer(RubySequencer):
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type = 'RubyHTMSequencer'
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cxx_class = 'gem5::ruby::HTMSequencer'
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cxx_header = "mem/ruby/system/HTMSequencer.hh"
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class DMASequencer(RubyPort):
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type = 'DMASequencer'
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cxx_header = "mem/ruby/system/DMASequencer.hh"
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cxx_class = 'gem5::ruby::DMASequencer'
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max_outstanding_requests = Param.Int(64, "max outstanding requests")
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