e69cce73c73445474e6a93637482630c282d9dae
A recent change got rid of the strict Master => Slave port relationship which used to be checked in python and instead left the checking up to C++. One major downside to this approach is that it was no longer obvious in the configuration what was supposed to be connected to what, and it still left the arbitrary and misleading MasterPort and SlavePort types in the Ethernet devices which could now connect with each other symmetrically but couldn't actually connect to an arbitrary MasterPort/SlavePort. This change exposes the base Port and VectorPort types, and makes them accept a "role" parameter in __init__ which used to be set directly by their subclasses. This role can be any string, and will be used later to check for compatiblity and to give a hint as to what can be connected to what in the SimObject definitions. To make the checks work with arbitrary compatible pairs, the base Port type now has a class method called compat() which accepts a pair of roles which will become mutually compatible, ie any port with the first role will be allowed to connect to any port with the second role, and vice versa. To be self compatible, the same role should be passed in for both parameters. To maintain compatibility, the MasterPort and SlavePort types are retained, but now they're nothing special and could have been set up in any arbitrary SimObject .py file. The same is true for MasterVectorPort and SlaveVectorPort. Also, since we can no longer assume that all edges in the dot graph of the config should start with a port with the MASTER role and end with a port with the SLAVE role, Ports now track an is_source property which says whether the arrow head should be surpressed at that end of the edge representing the connection. Change-Id: Ifcc6faab05e437ad87cd21f0ba613b09cf21c321 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18168 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
This is the gem5 simulator. The main website can be found at http://www.gem5.org A good starting point is http://www.gem5.org/Introduction, and for more information about building the simulator and getting started please see http://www.gem5.org/Documentation and http://www.gem5.org/Tutorials. To build gem5, you will need the following software: g++ or clang, Python (gem5 links in the Python interpreter), SCons, SWIG, zlib, m4, and lastly protobuf if you want trace capture and playback support. Please see http://www.gem5.org/Dependencies for more details concerning the minimum versions of the aforementioned tools. Once you have all dependencies resolved, type 'scons build/<ARCH>/gem5.opt' where ARCH is one of ALPHA, ARM, NULL, MIPS, POWER, SPARC, or X86. This will build an optimized version of the gem5 binary (gem5.opt) for the the specified architecture. See http://www.gem5.org/Build_System for more details and options. With the simulator built, have a look at http://www.gem5.org/Running_gem5 for more information on how to use gem5. The basic source release includes these subdirectories: - configs: example simulation configuration scripts - ext: less-common external packages needed to build gem5 - src: source code of the gem5 simulator - system: source for some optional system software for simulated systems - tests: regression tests - util: useful utility programs and files To run full-system simulations, you will need compiled system firmware (console and PALcode for Alpha), kernel binaries and one or more disk images. Please see the gem5 download page for these items at http://www.gem5.org/Download If you have questions, please send mail to gem5-users@gem5.org Enjoy using gem5 and please share your modifications and extensions.
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