e1db67c4bd
This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
79 lines
2.8 KiB
Python
79 lines
2.8 KiB
Python
# Copyright (c) 2015 Jason Power
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This is the RISCV equivalent to `simple.py` (which is designed to run using the
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X86 ISA). More detailed documentation can be found in `simple.py`.
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"""
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import m5
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from m5.objects import *
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system = System()
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system.clk_domain = SrcClockDomain()
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system.clk_domain.clock = "1GHz"
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system.clk_domain.voltage_domain = VoltageDomain()
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system.mem_mode = "timing"
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system.mem_ranges = [AddrRange("512MiB")]
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system.cpu = RiscvTimingSimpleCPU()
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system.membus = SystemXBar()
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system.cpu.icache_port = system.membus.cpu_side_ports
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system.cpu.dcache_port = system.membus.cpu_side_ports
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system.cpu.createInterruptController()
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system.mem_ctrl = MemCtrl()
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system.mem_ctrl.dram = DDR3_1600_8x8()
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system.mem_ctrl.dram.range = system.mem_ranges[0]
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system.mem_ctrl.port = system.membus.mem_side_ports
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system.system_port = system.membus.cpu_side_ports
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thispath = os.path.dirname(os.path.realpath(__file__))
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binary = os.path.join(
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thispath,
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"../../../",
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"tests/test-progs/hello/bin/riscv/linux/hello",
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)
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system.workload = SEWorkload.init_compatible(binary)
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process = Process()
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process.cmd = [binary]
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system.cpu.workload = process
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system.cpu.createThreads()
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root = Root(full_system=False, system=system)
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m5.instantiate()
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print(f"Beginning simulation!")
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exit_event = m5.simulate()
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print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}")
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