e1db67c4bd
This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
438 lines
14 KiB
Python
438 lines
14 KiB
Python
# Copyright (c) 2016-2017,2019-2023 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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"""This script is the full system example script from the ARM
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Research Starter Kit on System Modeling. More information can be found
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at: http://www.arm.com/ResearchEnablement/SystemModeling
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"""
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import argparse
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import os
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import m5
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from m5.objects import *
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from m5.options import *
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from m5.util import addToPath
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from gem5.simulate.exit_event import ExitEvent
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m5.util.addToPath("../..")
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import devices
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import workloads
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from common import (
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MemConfig,
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ObjectList,
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SysPaths,
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)
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from common.cores.arm import (
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HPI,
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O3_ARM_v7a,
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)
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# Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
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# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
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# the cache class may be 'None' if the particular cache is not present.
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cpu_types = {
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"atomic": (AtomicSimpleCPU, None, None, None),
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"minor": (MinorCPU, devices.L1I, devices.L1D, devices.L2),
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"hpi": (HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, HPI.HPI_L2),
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"o3": (
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O3_ARM_v7a.O3_ARM_v7a_3,
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O3_ARM_v7a.O3_ARM_v7a_ICache,
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O3_ARM_v7a.O3_ARM_v7a_DCache,
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O3_ARM_v7a.O3_ARM_v7aL2,
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),
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}
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pmu_control_events = {
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"enable": ExitEvent.PERF_COUNTER_ENABLE,
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"disable": ExitEvent.PERF_COUNTER_DISABLE,
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"reset": ExitEvent.PERF_COUNTER_RESET,
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}
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pmu_interrupt_events = {
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"interrupt": ExitEvent.PERF_COUNTER_INTERRUPT,
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}
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pmu_stats_events = dict(**pmu_control_events, **pmu_interrupt_events)
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def create_cow_image(name):
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"""Helper function to create a Copy-on-Write disk image"""
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image = CowDiskImage()
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image.child.image_file = name
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return image
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def create(args):
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"""Create and configure the system object."""
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if args.readfile and not os.path.isfile(args.readfile):
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print(f"Error: Bootscript {args.readfile} does not exist")
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sys.exit(1)
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object_file = args.kernel if args.kernel else ""
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cpu_class = cpu_types[args.cpu][0]
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mem_mode = cpu_class.memory_mode()
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# Only simulate caches when using a timing CPU (e.g., the HPI model)
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want_caches = True if mem_mode == "timing" else False
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platform = ObjectList.platform_list.get(args.machine_type)
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system = devices.SimpleSystem(
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want_caches,
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args.mem_size,
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platform=platform(),
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mem_mode=mem_mode,
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readfile=args.readfile,
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)
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MemConfig.config_mem(args, system)
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if args.semi_enable:
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system.semihosting = ArmSemihosting(
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stdin=args.semi_stdin,
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stdout=args.semi_stdout,
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stderr=args.semi_stderr,
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files_root_dir=args.semi_path,
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cmd_line=" ".join([object_file] + args.args),
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)
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if args.disk_image:
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# Create a VirtIO block device for the system's boot
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# disk. Attach the disk image using gem5's Copy-on-Write
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# functionality to avoid writing changes to the stored copy of
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# the disk image.
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system.realview.vio[0].vio = VirtIOBlock(
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image=create_cow_image(args.disk_image)
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)
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# Wire up the system's memory system
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system.connect()
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# Add CPU clusters to the system
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system.cpu_cluster = [
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devices.ArmCpuCluster(
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system,
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args.num_cores,
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args.cpu_freq,
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"1.0V",
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*cpu_types[args.cpu],
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tarmac_gen=args.tarmac_gen,
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tarmac_dest=args.tarmac_dest,
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)
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]
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# Create a cache hierarchy for the cluster. We are assuming that
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# clusters have core-private L1 caches and an L2 that's shared
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# within the cluster.
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system.addCaches(want_caches, last_cache_level=2)
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# Setup gem5's minimal Linux boot loader.
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system.auto_reset_addr = True
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# Using GICv3
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if hasattr(system.realview.gic, "gicv4"):
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system.realview.gic.gicv4 = False
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system.highest_el_is_64 = True
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workload_class = workloads.workload_list.get(args.workload)
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system.workload = workload_class(object_file, system)
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if args.with_pmu:
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enabled_pmu_events = {
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*args.pmu_dump_stats_on,
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*args.pmu_reset_stats_on,
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}
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exit_sim_on_control = bool(
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enabled_pmu_events & set(pmu_control_events.keys())
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)
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exit_sim_on_interrupt = bool(
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enabled_pmu_events & set(pmu_interrupt_events.keys())
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)
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for cluster in system.cpu_cluster:
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interrupt_numbers = [args.pmu_ppi_number] * len(cluster)
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cluster.addPMUs(
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interrupt_numbers,
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exit_sim_on_control=exit_sim_on_control,
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exit_sim_on_interrupt=exit_sim_on_interrupt,
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)
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if args.exit_on_uart_eot:
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for uart in system.realview.uart:
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uart.end_on_eot = True
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return system
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def run(args):
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cptdir = m5.options.outdir
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if args.checkpoint:
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print(f"Checkpoint directory: {cptdir}")
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pmu_exit_msgs = tuple(evt.value for evt in pmu_stats_events.values())
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pmu_stats_dump_msgs = tuple(
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pmu_stats_events[evt].value for evt in set(args.pmu_dump_stats_on)
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)
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pmu_stats_reset_msgs = tuple(
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pmu_stats_events[evt].value for evt in set(args.pmu_reset_stats_on)
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)
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while True:
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event = m5.simulate()
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exit_msg = event.getCause()
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if exit_msg == ExitEvent.CHECKPOINT.value:
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print(f"Dropping checkpoint at tick {m5.curTick():d}")
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cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick())
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m5.checkpoint(os.path.join(cpt_dir))
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print("Checkpoint done.")
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elif exit_msg in pmu_exit_msgs:
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if exit_msg in pmu_stats_dump_msgs:
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print(
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f"Dumping stats at tick {m5.curTick():d}, "
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f"due to {exit_msg}"
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)
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m5.stats.dump()
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if exit_msg in pmu_stats_reset_msgs:
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print(
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f"Resetting stats at tick {m5.curTick():d}, "
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f"due to {exit_msg}"
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)
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m5.stats.reset()
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else:
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print(f"{exit_msg} ({event.getCode()}) @ {m5.curTick()}")
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break
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def arm_ppi_arg(int_num: int) -> int:
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"""Argparse argument parser for valid Arm PPI numbers."""
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# PPIs (1056 <= int_num <= 1119) are not yet supported by gem5
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int_num = int(int_num)
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if 16 <= int_num <= 31:
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return int_num
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raise ValueError(f"{int_num} is not a valid Arm PPI number")
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def main():
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parser = argparse.ArgumentParser(epilog=__doc__)
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parser.add_argument(
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"--kernel", type=str, default=None, help="Binary to run"
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)
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parser.add_argument(
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"--workload",
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type=str,
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default="ArmBaremetal",
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choices=workloads.workload_list.get_names(),
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help="Workload type",
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)
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parser.add_argument(
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"--disk-image", type=str, default=None, help="Disk to instantiate"
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)
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parser.add_argument(
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"--readfile",
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type=str,
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default="",
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help="File to return with the m5 readfile command",
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)
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parser.add_argument(
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"--cpu",
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type=str,
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choices=list(cpu_types.keys()),
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default="atomic",
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help="CPU model to use",
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)
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parser.add_argument("--cpu-freq", type=str, default="4GHz")
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parser.add_argument(
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"--num-cores", type=int, default=1, help="Number of CPU cores"
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)
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parser.add_argument(
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"--machine-type",
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type=str,
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choices=ObjectList.platform_list.get_names(),
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default="VExpress_GEM5_V2",
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help="Hardware platform class",
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)
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parser.add_argument(
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"--mem-type",
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default="DDR3_1600_8x8",
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choices=ObjectList.mem_list.get_names(),
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help="type of memory to use",
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)
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parser.add_argument(
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"--mem-channels", type=int, default=1, help="number of memory channels"
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)
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parser.add_argument(
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"--mem-ranks",
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type=int,
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default=None,
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help="number of memory ranks per channel",
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)
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parser.add_argument(
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"--mem-size",
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action="store",
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type=str,
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default="2GiB",
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help="Specify the physical memory size",
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)
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parser.add_argument("--checkpoint", action="store_true")
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parser.add_argument("--restore", type=str, default=None)
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parser.add_argument(
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"--tarmac-gen",
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action="store_true",
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help="Write a Tarmac trace.",
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)
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parser.add_argument(
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"--tarmac-dest",
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choices=TarmacDump.vals,
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default="stdoutput",
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help="Destination for the Tarmac trace output. [Default: stdoutput]",
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)
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parser.add_argument(
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"--with-pmu",
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action="store_true",
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help="Add a PMU to each core in the cluster.",
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)
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parser.add_argument(
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"--pmu-ppi-number",
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type=arm_ppi_arg,
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default=23,
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help="The number of the PPI to use to connect each PMU to its core. "
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"Must be an integer and a valid PPI number (16 <= int_num <= 31).",
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)
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parser.add_argument(
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"--pmu-dump-stats-on",
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type=str,
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default=[],
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action="append",
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choices=pmu_stats_events.keys(),
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help="Specify the PMU events on which to dump the gem5 stats. "
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"This option may be specified multiple times to enable multiple "
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"PMU events.",
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)
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parser.add_argument(
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"--pmu-reset-stats-on",
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type=str,
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default=[],
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action="append",
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choices=pmu_stats_events.keys(),
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help="Specify the PMU events on which to reset the gem5 stats. "
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"This option may be specified multiple times to enable multiple "
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"PMU events.",
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)
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parser.add_argument(
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"--exit-on-uart-eot",
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action="store_true",
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help="Exit simulation if any of the UARTs receive an EOT. Many "
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"workloads signal termination by sending an EOT character.",
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)
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parser.add_argument(
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"--dtb-gen",
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action="store_true",
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help="Doesn't run simulation, it generates a DTB only",
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)
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parser.add_argument(
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"--semi-enable", action="store_true", help="Enable semihosting support"
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)
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parser.add_argument(
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"--semi-stdin",
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type=str,
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default="stdin",
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help="Standard input for semihosting (default: gem5's stdin)",
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)
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parser.add_argument(
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"--semi-stdout",
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type=str,
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default="stdout",
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help="Standard output for semihosting (default: gem5's stdout)",
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)
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parser.add_argument(
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"--semi-stderr",
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type=str,
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default="stderr",
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help="Standard error for semihosting (default: gem5's stderr)",
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)
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parser.add_argument(
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"--semi-path",
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type=str,
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default="",
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help=("Search path for files to be loaded through Arm Semihosting"),
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)
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parser.add_argument(
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"args",
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default=[],
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nargs="*",
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help="Semihosting arguments to pass to benchmark",
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)
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parser.add_argument(
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"-P",
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"--param",
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action="append",
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default=[],
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help="Set a SimObject parameter relative to the root node. "
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"An extended Python multi range slicing syntax can be used "
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"for arrays. For example: "
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"'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
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"sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
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"Direct parameters of the root object are not accessible, "
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"only parameters of its children.",
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)
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args = parser.parse_args()
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root = Root(full_system=True)
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root.system = create(args)
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root.apply_config(args.param)
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if args.restore is not None:
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m5.instantiate(args.restore)
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else:
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m5.instantiate()
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if args.dtb_gen:
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# No run, autogenerate DTB and exit
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root.system.generateDtb(os.path.join(m5.options.outdir, "system.dtb"))
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else:
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run(args)
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if __name__ == "__m5_main__":
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main()
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