773368d68d
Create a directory called "regs" which holds files, primarily headers, related to registers, with the exception of registers.hh. Hopefully registers.hh will go away in the not too distant future, removing this exception. Change-Id: I631423c2b09bbcd14b20001380270718aeca619e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41737 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
833 lines
25 KiB
C++
833 lines
25 KiB
C++
/*
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* Copyright (c) 2019 Metempsy Technology LSC
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/arm/self_debug.hh"
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#include "arch/arm/faults.hh"
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#include "arch/arm/regs/misc_types.hh"
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#include "base/bitfield.hh"
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using namespace ArmISA;
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Fault
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SelfDebug::testDebug(ThreadContext *tc, const RequestPtr &req,
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BaseTLB::Mode mode)
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{
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Fault fault = NoFault;
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if (mode == BaseTLB::Execute) {
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const bool d_step = softStep->advanceSS(tc);
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if (!d_step) {
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fault = testVectorCatch(tc, req->getVaddr(), nullptr);
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if (fault == NoFault)
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fault = testBreakPoints(tc, req->getVaddr());
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}
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} else if (!req->isCacheMaintenance() ||
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(req->isCacheInvalidate() && !req->isCacheClean())) {
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bool md = mode == BaseTLB::Write ? true: false;
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fault = testWatchPoints(tc, req->getVaddr(), md,
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req->isAtomic(),
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req->getSize(),
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req->isCacheMaintenance());
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}
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return fault;
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}
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Fault
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SelfDebug::testBreakPoints(ThreadContext *tc, Addr vaddr)
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{
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if (!mde)
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return NoFault;
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setAArch32(tc);
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to32 = targetAArch32(tc);
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init(tc);
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if (!isDebugEnabled(tc))
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return NoFault;
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ExceptionLevel el = (ExceptionLevel) currEL(tc);
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for (auto &p: arBrkPoints){
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PCState pcst = tc->pcState();
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Addr pc = vaddr;
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if (pcst.itstate() != 0x0)
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pc = pcst.pc();
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if (p.enable && p.isActive(pc) &&(!to32 || !p.onUse)) {
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const DBGBCR ctr = p.getControlReg(tc);
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if (p.isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pmc)) {
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bool debug = p.test(tc, pc, el, ctr, false);
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if (debug){
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if (to32)
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p.onUse = true;
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return triggerException(tc, pc);
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}
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}
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}
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}
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return NoFault;
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}
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Fault
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SelfDebug::triggerException(ThreadContext *tc, Addr vaddr)
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{
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if (to32) {
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return std::make_shared<PrefetchAbort>(vaddr,
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ArmFault::DebugEvent, false,
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ArmFault::UnknownTran,
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ArmFault::BRKPOINT);
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} else {
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return std::make_shared<HardwareBreakpoint>(vaddr, 0x22);
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}
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}
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Fault
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SelfDebug::testWatchPoints(ThreadContext *tc, Addr vaddr, bool write,
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bool atomic, unsigned size, bool cm)
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{
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setAArch32(tc);
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to32 = targetAArch32(tc);
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if (!initialized)
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init(tc);
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if (!isDebugEnabled(tc) || !mde)
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return NoFault;
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ExceptionLevel el = (ExceptionLevel) currEL(tc);
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int idxtmp = -1;
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for (auto &p: arWatchPoints){
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idxtmp ++;
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if (p.enable) {
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bool debug = p.test(tc, vaddr, el, write, atomic, size);
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if (debug){
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return triggerWatchpointException(tc, vaddr, write, cm);
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}
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}
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}
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return NoFault;
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}
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Fault
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SelfDebug::triggerWatchpointException(ThreadContext *tc, Addr vaddr,
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bool write, bool cm)
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{
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if (to32) {
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ArmFault::DebugType d = cm? ArmFault::WPOINT_CM:
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ArmFault::WPOINT_NOCM;
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return std::make_shared<DataAbort>(vaddr,
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TlbEntry::DomainType::NoAccess,
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write, ArmFault::DebugEvent, cm,
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ArmFault::UnknownTran, d);
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} else {
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return std::make_shared<Watchpoint>(0, vaddr, write, cm);
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}
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}
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bool
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SelfDebug::isDebugEnabledForEL64(ThreadContext *tc, ExceptionLevel el,
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bool secure, bool mask)
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{
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bool route_to_el2 = ArmSystem::haveEL(tc, EL2) &&
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(!secure || HaveSecureEL2Ext(tc)) && enableTdeTge;
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ExceptionLevel target_el = route_to_el2 ? EL2 : EL1;
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if (oslk || (sdd && secure && ArmSystem::haveEL(tc, EL3))) {
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return false;
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}
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if (el == target_el) {
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return kde && !mask;
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} else {
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return target_el > el;
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}
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}
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bool
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SelfDebug::isDebugEnabledForEL32(ThreadContext *tc, ExceptionLevel el,
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bool secure, bool mask)
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{
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if (el == EL0 && !ELStateUsingAArch32(tc, EL1, secure)) {
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return isDebugEnabledForEL64(tc, el, secure, mask);
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}
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if (oslk) {
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return false;
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}
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bool enabled;
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if (secure && ArmSystem::haveEL(tc, EL3)) {
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// We ignore the check for invasive External debug checking SPIDEN
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// and DBGEN signals. They are not implemented
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bool spd32 = bits(tc->readMiscReg(MISCREG_MDCR_EL3), 14);
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enabled = spd32;
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bool suiden = bits(tc->readMiscReg(MISCREG_SDER), 0);
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enabled = el == EL0 ? (enabled || suiden) : enabled;
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} else {
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enabled = el != EL2;
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}
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return enabled;
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}
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bool
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BrkPoint::testLinkedBk(ThreadContext *tc, Addr vaddr, ExceptionLevel el)
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{
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bool debug = false;
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const DBGBCR ctr = getControlReg(tc);
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if ((ctr.bt & 0x1) && enable) {
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debug = test(tc, vaddr, el, ctr, true);
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}
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return debug;
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}
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bool
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BrkPoint::test(ThreadContext *tc, Addr pc, ExceptionLevel el, DBGBCR ctr,
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bool from_link)
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{
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bool v = false;
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switch (ctr.bt) {
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case 0x0:
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v = testAddrMatch(tc, pc, ctr.bas);
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break;
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case 0x1:
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v = testAddrMatch(tc, pc, ctr.bas); // linked
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if (v) {
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v = (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, pc, el);
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}
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break;
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case 0x2:
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{
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bool host = ELIsInHost(tc, el);
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v = testContextMatch(tc, !host, true);
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}
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break;
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case 0x3:
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if (from_link){
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bool host = ELIsInHost(tc, el);
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v = testContextMatch(tc, !host, true);
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}
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break;
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case 0x4:
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v = testAddrMissMatch(tc, pc, ctr.bas);
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break;
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case 0x5:
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v = testAddrMissMatch(tc, pc, ctr.bas); // linked
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if (v && !from_link)
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v = v && (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, pc, el);
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break;
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case 0x6:
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if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el))
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v = testContextMatch(tc, true);
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break;
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case 0x7:
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if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el) && from_link)
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v = testContextMatch(tc, true);
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break;
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case 0x8:
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if (EL2Enabled(tc) && !ELIsInHost(tc, el)) {
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v = testVMIDMatch(tc);
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}
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break;
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case 0x9:
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if (from_link && EL2Enabled(tc) && !ELIsInHost(tc, el)) {
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v = testVMIDMatch(tc);
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}
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break;
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case 0xa:
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if (EL2Enabled(tc) && !ELIsInHost(tc, el)) {
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v = testContextMatch(tc, true);
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if (v && !from_link)
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v = v && testVMIDMatch(tc);
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}
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break;
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case 0xb:
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if (from_link && EL2Enabled(tc) && !ELIsInHost(tc, el)) {
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v = testContextMatch(tc, true);
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v = v && testVMIDMatch(tc);
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}
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break;
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case 0xc:
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if (HaveVirtHostExt(tc) && (!isSecure(tc)|| HaveSecureEL2Ext(tc)))
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v = testContextMatch(tc, false);
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break;
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case 0xd:
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if (HaveVirtHostExt(tc) && from_link &&
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(!isSecure(tc)|| HaveSecureEL2Ext(tc))) {
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v = testContextMatch(tc, false);
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}
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break;
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case 0xe:
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if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el) &&
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(!isSecure(tc)|| HaveSecureEL2Ext(tc))) {
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v = testContextMatch(tc, true); // CONTEXTIDR_EL1
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v = v && testContextMatch(tc, false); // CONTEXTIDR_EL2
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}
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break;
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case 0xf:
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if (HaveVirtHostExt(tc) && !ELIsInHost(tc, el) && from_link &&
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(!isSecure(tc)|| HaveSecureEL2Ext(tc))) {
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v = testContextMatch(tc, true); // CONTEXTIDR_EL1
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v = v && testContextMatch(tc, false); // CONTEXTIDR_EL2
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}
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break;
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default:
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break;
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}
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return v;
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}
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void
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SelfDebug::init(ThreadContext *tc)
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{
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if (initialized)
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return;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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aarch32 = cpsr.width == 1;
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const AA64DFR0 dfr = tc->readMiscReg(MISCREG_ID_AA64DFR0_EL1);
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const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
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const AA64MMFR1 mm_fr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
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for (int i = 0; i <= dfr.brps; i++) {
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const bool isctxaw = i >= (dfr.brps - dfr.ctx_cmps);
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BrkPoint bkp = BrkPoint((MiscRegIndex)(MISCREG_DBGBCR0_EL1 + i),
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(MiscRegIndex)(MISCREG_DBGBVR0_EL1 + i),
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this, isctxaw, (bool)mm_fr2.varange,
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mm_fr1.vmidbits, aarch32);
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const DBGBCR ctr = tc->readMiscReg(MISCREG_DBGBCR0_EL1 + i);
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bkp.updateControl(ctr);
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arBrkPoints.push_back(bkp);
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}
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for (int i = 0; i <= dfr.wrps; i++) {
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WatchPoint wtp = WatchPoint((MiscRegIndex)(MISCREG_DBGWCR0 + i),
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(MiscRegIndex)(MISCREG_DBGWVR0 + i),
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this, (bool)mm_fr2.varange, aarch32);
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const DBGWCR ctr = tc->readMiscReg(MISCREG_DBGWCR0 + i);
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wtp.updateControl(ctr);
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arWatchPoints.push_back(wtp);
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}
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initialized = true;
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RegVal oslar_el1 = tc->readMiscReg(MISCREG_OSLAR_EL1);
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updateOSLock(oslar_el1);
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// Initialize preloaded control booleans
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uint64_t mdscr_el1 = tc->readMiscReg(MISCREG_MDSCR_EL1);
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setMDSCRvals(mdscr_el1);
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const uint64_t mdcr_el3 = tc->readMiscReg(MISCREG_MDCR_EL3);
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setbSDD(mdcr_el3);
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const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
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const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
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setenableTDETGE(hcr, mdcr);
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// Enable Vector Catch Exceptions
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const DEVID dvid = tc->readMiscReg(MISCREG_DBGDEVID0);
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vcExcpt = new VectorCatch(dvid.vectorcatch==0x0, this);
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}
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bool
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BrkPoint::testAddrMatch(ThreadContext *tc, Addr in_pc, uint8_t bas)
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{
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Addr pc_tocmp = getAddrfromReg(tc);
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Addr pc = bits(in_pc, maxAddrSize, 2);
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bool prs = true;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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bool thumb = cpsr.t;
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if (thumb) {
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if (bas == 0xc)
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prs = bits(in_pc, 1, 0) == 0x2;
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else if (bas == 0x3)
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prs = bits(in_pc, 1, 0) == 0x0;
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}
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return (pc == pc_tocmp) && prs;
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}
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bool
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BrkPoint::testAddrMissMatch(ThreadContext *tc, Addr in_pc, uint8_t bas)
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{
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if (bas == 0x0)
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return true;
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Addr pc_tocmp = getAddrfromReg(tc);
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Addr pc = bits(in_pc, maxAddrSize, 2);
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bool prs = false;
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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bool thumb = cpsr.t;
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if (thumb) {
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if (bas == 0xc)
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prs = bits(in_pc, 1, 0) == 0x2;
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else if (bas == 0x3)
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prs = bits(in_pc, 1, 0) == 0x0;
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}
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return (pc != pc_tocmp) && !prs;
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}
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bool
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BrkPoint::testContextMatch(ThreadContext *tc, bool ctx1)
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{
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return testContextMatch(tc, ctx1, ctx1);
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}
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bool
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BrkPoint::testContextMatch(ThreadContext *tc, bool ctx1, bool low_ctx)
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{
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if (!isCntxtAware)
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return false;
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MiscRegIndex miscridx;
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ExceptionLevel el = currEL(tc);
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bool a32 = conf->isAArch32();
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if (ctx1) {
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miscridx = a32? MISCREG_CONTEXTIDR : MISCREG_CONTEXTIDR_EL1;
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if ((el == EL3 && !a32) || el == EL2)
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return false;
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} else {
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miscridx = MISCREG_CONTEXTIDR_EL2;
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if (el == EL2 && a32)
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return false;
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}
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RegVal ctxid = bits(tc->readMiscReg(miscridx), 31, 0);
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RegVal v = getContextfromReg(tc, low_ctx);
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return (v == ctxid);
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}
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bool
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BrkPoint::testVMIDMatch(ThreadContext *tc)
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{
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uint32_t vmid_index = 55;
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if (VMID16enabled)
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vmid_index = 63;
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ExceptionLevel el = currEL(tc);
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if (el == EL2)
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return false;
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uint32_t vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), vmid_index, 48);
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uint32_t v = getVMIDfromReg(tc);
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return (v == vmid);
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}
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bool
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BrkPoint::isEnabled(ThreadContext *tc, ExceptionLevel el,
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uint8_t hmc, uint8_t ssc, uint8_t pmc)
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{
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bool v;
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bool aarch32 = conf->isAArch32();
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bool no_el2 = !ArmSystem::haveEL(tc, EL2);
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bool no_el3 = !ArmSystem::haveEL(tc, EL3);
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if (no_el3 && !no_el2 && (ssc == 0x1 || ssc == 0x2) &&
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!(hmc && ssc == 0x1 && pmc == 0x0)) {
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return false;
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} else if (no_el3 && no_el2 && (hmc != 0x0 || ssc != 0x0) &&
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!(!aarch32 && ((hmc && ssc == 0x1 && pmc == 0x0) || ssc == 0x3))) {
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return false;
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} else if (no_el2 && hmc && ssc == 0x3 && pmc == 0x0) {
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return false;
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} else if (ssc == 0x11 && pmc == 0x1 &&
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!(!aarch32 && hmc && ssc == 0x3 && pmc == 0x0)) {
|
|
// AND secureEL2 not implemented
|
|
return false;
|
|
} else if (hmc && ssc == 0x1 && pmc == 0x0) {
|
|
//AND secureEL2 not implemented
|
|
return false;
|
|
}
|
|
switch (el) {
|
|
case EL0:
|
|
v = (pmc == 0x3) || (pmc == 0x2 && hmc == 0x0);
|
|
if (aarch32)
|
|
v = v || (pmc == 0x0 && ssc != 0x3 && hmc == 0x0);
|
|
if (v && ssc == 0x3)
|
|
panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
|
|
break;
|
|
case EL1:
|
|
v = (pmc == 0x3) || (pmc == 0x1);
|
|
if (aarch32)
|
|
v = v || (pmc == 0x0 && hmc == 0x0 && ssc !=0x3);
|
|
break;
|
|
case EL2:
|
|
v = (ssc == 0x3) ||
|
|
((hmc == 0x1) && !((ssc == 0x2) && (pmc == 0x0)));
|
|
if (v && pmc == 0x2)
|
|
panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
|
|
break;
|
|
case EL3:
|
|
if (ssc == 0x1)
|
|
panic("Unexpected EL in SelfDebug::isDebugEnabled.\n");
|
|
v = (hmc == 0x1) & (ssc != 0x3);
|
|
break;
|
|
default:
|
|
panic("Unexpected EL %d in BrkPoint::isEnabled.\n", el);
|
|
}
|
|
return v && SelfDebug::securityStateMatch(tc, ssc, hmc || !aarch32);
|
|
}
|
|
|
|
uint32_t
|
|
BrkPoint::getVMIDfromReg(ThreadContext *tc)
|
|
{
|
|
uint32_t vmid_index = 39;
|
|
if (VMID16enabled)
|
|
vmid_index = 47;
|
|
return bits(tc->readMiscReg(valRegIndex), vmid_index, 32);
|
|
}
|
|
|
|
|
|
bool
|
|
WatchPoint::isEnabled(ThreadContext* tc, ExceptionLevel el,
|
|
bool hmc, uint8_t ssc, uint8_t pac)
|
|
{
|
|
|
|
bool v;
|
|
bool aarch32 = conf->isAArch32();
|
|
bool no_el2 = !ArmSystem::haveEL(tc, EL2);
|
|
bool no_el3 = !ArmSystem::haveEL(tc, EL3);
|
|
|
|
if (aarch32) {
|
|
// WatchPoint PL2 using aarch32 is disabled except for
|
|
// debug state. Check G2-5395 table G2-15.
|
|
if (el == EL2)
|
|
return false;
|
|
if (no_el3) {
|
|
if (ssc == 0x01 || ssc == 0x02 ){
|
|
return false;
|
|
} else if (no_el2 &&
|
|
((!hmc && ssc == 0x3) || (hmc && ssc == 0x0))) {
|
|
return false;
|
|
}
|
|
}
|
|
if (no_el2 && hmc && ssc == 0x03 && pac == 0)
|
|
return false;
|
|
}
|
|
switch (el) {
|
|
case EL0:
|
|
v = (pac == 0x3 || (pac == 0x2 && !hmc && ssc != 0x3));
|
|
break;
|
|
case EL1:
|
|
v = (pac == 0x1 || pac == 0x3);
|
|
break;
|
|
case EL2:
|
|
v = (hmc && (ssc != 0x2 || pac != 0x0));
|
|
break;
|
|
case EL3:
|
|
v = (hmc && (ssc == 0x2 ||
|
|
(ssc == 0x1 && (pac == 0x1 || pac == 0x3))));
|
|
break;
|
|
default:
|
|
panic("Unexpected EL in WatchPoint::isEnabled.\n");
|
|
}
|
|
return v && SelfDebug::securityStateMatch(tc, ssc, hmc);
|
|
}
|
|
|
|
bool
|
|
WatchPoint::test(ThreadContext *tc, Addr addr, ExceptionLevel el, bool& wrt,
|
|
bool atomic, unsigned size)
|
|
{
|
|
|
|
bool v = false;
|
|
const DBGWCR ctr = tc->readMiscReg(ctrlRegIndex);
|
|
if (isEnabled(tc, el, ctr.hmc, ctr.ssc, ctr.pac) &&
|
|
((wrt && (ctr.lsv & 0x2)) || (!wrt && (ctr.lsv & 0x1)) || atomic)) {
|
|
v = compareAddress(tc, addr, ctr.bas, ctr.mask, size);
|
|
if (ctr.wt) {
|
|
v = v && (conf->getBrkPoint(ctr.lbn))->testLinkedBk(tc, addr, el);
|
|
}
|
|
}
|
|
if (atomic && (ctr.lsv & 0x1)) {
|
|
wrt = false;
|
|
}
|
|
return v;
|
|
}
|
|
|
|
bool
|
|
WatchPoint::compareAddress(ThreadContext *tc, Addr in_addr, uint8_t bas,
|
|
uint8_t mask, unsigned size)
|
|
{
|
|
Addr addr_tocmp = getAddrfromReg(tc);
|
|
int maxbits = isDoubleAligned(addr_tocmp) ? 4: 8;
|
|
int bottom = isDoubleAligned(addr_tocmp) ? 2: 3;
|
|
Addr addr = bits(in_addr, maxAddrSize, 0);
|
|
|
|
if (bas == 0x0)
|
|
return false;
|
|
|
|
if (mask == 0x0) {
|
|
for (int i = 0; i < maxbits; i++) {
|
|
uint8_t bas_m = 0x1 << i;
|
|
uint8_t masked_bas = bas & bas_m;
|
|
if (masked_bas == bas_m) {
|
|
uint8_t off = log2(masked_bas);
|
|
Addr cmpaddr = addr_tocmp | off;
|
|
for (int j = 0; j < size; j++) {
|
|
if ((addr + j) == cmpaddr) {
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
} else {
|
|
bool v = false;
|
|
for (int j = 0; j < size; j++) {
|
|
Addr compaddr;
|
|
if (mask > bottom) {
|
|
addr = bits((in_addr+j), maxAddrSize, mask);
|
|
compaddr = bits(addr_tocmp, maxAddrSize, mask);
|
|
} else {
|
|
addr = bits((in_addr+j), maxAddrSize, bottom);
|
|
compaddr = bits(addr_tocmp, maxAddrSize, bottom);
|
|
}
|
|
v = v || (addr == compaddr);
|
|
}
|
|
return v;
|
|
}
|
|
}
|
|
|
|
bool
|
|
SoftwareStep::debugExceptionReturnSS(ThreadContext *tc, CPSR spsr,
|
|
ExceptionLevel dest)
|
|
{
|
|
bool SS_bit = false;
|
|
bool enabled_src = false;
|
|
if (bSS) {
|
|
enabled_src = conf->isDebugEnabled(tc);
|
|
|
|
bool enabled_dst = false;
|
|
bool secure = isSecureBelowEL3(tc) || dest == EL3;
|
|
if (spsr.width) {
|
|
enabled_dst = conf->isDebugEnabledForEL32(tc, dest, secure,
|
|
spsr.d == 1);
|
|
} else {
|
|
enabled_dst = conf->isDebugEnabledForEL64(tc, dest, secure,
|
|
spsr.d == 1);
|
|
}
|
|
ExceptionLevel ELd = debugTargetFrom(tc, secure);
|
|
|
|
if (!ELIs32(tc, ELd) && !enabled_src && enabled_dst) {
|
|
SS_bit = spsr.ss;
|
|
if (SS_bit == 0x0) {
|
|
stateSS = ACTIVE_PENDING_STATE;
|
|
} else {
|
|
stateSS = ACTIVE_NOT_PENDING_STATE;
|
|
}
|
|
}
|
|
}
|
|
return SS_bit;
|
|
}
|
|
|
|
bool
|
|
SoftwareStep::advanceSS(ThreadContext * tc)
|
|
{
|
|
|
|
PCState pc = tc->pcState();
|
|
bool res = false;
|
|
switch (stateSS) {
|
|
case INACTIVE_STATE:
|
|
pc.debugStep(false);
|
|
break;
|
|
|
|
case ACTIVE_NOT_PENDING_STATE:
|
|
pc.debugStep(false);
|
|
if (cpsrD == 1 || !bSS) {
|
|
stateSS = INACTIVE_STATE;
|
|
} else {
|
|
pc.stepped(true);
|
|
stateSS = ACTIVE_PENDING_STATE;
|
|
tc->pcState(pc);
|
|
}
|
|
break;
|
|
|
|
case ACTIVE_PENDING_STATE:
|
|
if (!cpsrD && bSS) {
|
|
pc.debugStep(true);
|
|
res = true;
|
|
tc->pcState(pc);
|
|
}
|
|
stateSS = INACTIVE_STATE;
|
|
clearLdx();
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
return res;
|
|
}
|
|
|
|
Fault
|
|
SelfDebug::testVectorCatch(ThreadContext *tc, Addr addr,
|
|
ArmFault *fault)
|
|
{
|
|
|
|
setAArch32(tc);
|
|
to32 = targetAArch32(tc);
|
|
if (!initialized)
|
|
init(tc);
|
|
if (!isDebugEnabled(tc) || !mde || !aarch32)
|
|
return NoFault;
|
|
|
|
ExceptionLevel el = (ExceptionLevel) currEL(tc);
|
|
bool debug;
|
|
if (fault == nullptr)
|
|
debug = vcExcpt->addressMatching(tc, addr, el);
|
|
else
|
|
debug = vcExcpt->exceptionTrapping(tc, el, fault);
|
|
if (debug) {
|
|
if (enableTdeTge) {
|
|
return std::make_shared<HypervisorTrap>(0, 0x22,
|
|
EC_PREFETCH_ABORT_TO_HYP);
|
|
} else {
|
|
return std::make_shared<PrefetchAbort>(addr,
|
|
ArmFault::DebugEvent, false,
|
|
ArmFault::UnknownTran,
|
|
ArmFault::VECTORCATCH);
|
|
}
|
|
}
|
|
|
|
return NoFault;
|
|
}
|
|
|
|
bool
|
|
VectorCatch::addressMatching(ThreadContext *tc, Addr addr, ExceptionLevel el)
|
|
{
|
|
// Each bit position in this string corresponds to a bit in DBGVCR
|
|
// and an exception vector.
|
|
bool enabled;
|
|
if (conf->isAArch32() && ELIs32(tc, EL1) &&
|
|
(addr & 0x3) == 0 && el != EL2 ) {
|
|
|
|
DBGVCR match_word = 0x0;
|
|
|
|
Addr vbase = getVectorBase(tc, false);
|
|
Addr vaddress = addr & ~ 0x1f;
|
|
Addr low_addr = bits(addr, 5, 2);
|
|
if (vaddress == vbase) {
|
|
if (ArmSystem::haveEL(tc, EL3) && !isSecure(tc)) {
|
|
uint32_t bmask = 1UL << (low_addr + 24);
|
|
match_word = match_word | (DBGVCR) bmask;
|
|
// Non-secure vectors
|
|
} else {
|
|
uint32_t bmask = 1UL << (low_addr);
|
|
match_word = match_word | (DBGVCR) bmask;
|
|
// Secure vectors (or no EL3)
|
|
}
|
|
}
|
|
uint32_t mvbase = getVectorBase(tc, true);
|
|
if (ArmSystem::haveEL(tc, EL3) && ELIs32(tc, EL3) &&
|
|
isSecure(tc) && (vaddress == mvbase)) {
|
|
uint32_t bmask = 1UL << (low_addr + 8);
|
|
match_word = match_word | (DBGVCR) bmask;
|
|
// Monitor vectors
|
|
}
|
|
|
|
DBGVCR mask;
|
|
|
|
// Mask out bits not corresponding to vectors.
|
|
if (!ArmSystem::haveEL(tc, EL3)) {
|
|
mask = (DBGVCR) 0xDE;
|
|
} else if (!ELIs32(tc, EL3)) {
|
|
mask = (DBGVCR) 0xDE0000DE;
|
|
} else {
|
|
mask = (DBGVCR) 0xDE00DEDE;
|
|
}
|
|
DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
|
|
match_word = match_word & dbgvcr & mask;
|
|
enabled = match_word != 0x0;
|
|
// Check for UNPREDICTABLE case - match on Prefetch Abort and
|
|
// Data Abort vectors
|
|
ExceptionLevel ELd = debugTargetFrom(tc, isSecure(tc));
|
|
if (((match_word & 0x18001818) != 0x0) && ELd == el) {
|
|
enabled = false;
|
|
}
|
|
} else {
|
|
enabled = false;
|
|
}
|
|
return enabled;
|
|
}
|
|
|
|
bool
|
|
VectorCatch::exceptionTrapping(ThreadContext *tc, ExceptionLevel el,
|
|
ArmFault* fault)
|
|
{
|
|
if (conf->isAArch32() && ELIs32(tc, EL1) && el != EL2) {
|
|
|
|
DBGVCR dbgvcr = tc->readMiscReg(MISCREG_DBGVCR);
|
|
DBGVCR match_type = fault->vectorCatchFlag();
|
|
DBGVCR mask;
|
|
|
|
if (!ArmSystem::haveEL(tc, EL3)) {
|
|
mask = (DBGVCR) 0xDE;
|
|
} else if (ELIs32(tc, EL3) && fault->getToMode() == MODE_MON) {
|
|
mask = (DBGVCR) 0x0000DE00;
|
|
} else {
|
|
if (isSecure(tc))
|
|
mask = (DBGVCR) 0x000000DE;
|
|
else
|
|
mask = (DBGVCR) 0xDE000000;
|
|
}
|
|
match_type = match_type & mask & dbgvcr;
|
|
|
|
if (match_type != 0x0) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|