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gem5/src/sim
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Giacomo Travaglini 5187a24d49 sim,cpu,mem,arch: Introduced MasterInfo data structure 
With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.

Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-27 16:00:28 +00:00
..
power
docs: Fix power model doxygen
2018-04-20 15:59:35 +00:00
probe
mem: Record the request master ID in the PacketInfo structure.
2017-09-25 21:13:24 +00:00
arguments.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
arguments.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
async.cc
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
async.hh
base: Fix race in PollQueue and remove SIGALRM workaround
2013-11-29 14:36:10 +01:00
aux_vector.cc
syscall_emul: [patch 8/22] refactor process class
2016-11-09 14:27:41 -06:00
aux_vector.hh
syscall_emul: [patch 8/22] refactor process class
2016-11-09 14:27:41 -06:00
backtrace_glibc.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
backtrace_none.cc
sim: Add support for generating back traces on errors
2015-12-04 00:12:58 +00:00
backtrace.hh
sim: Add support for generating back traces on errors
2015-12-04 00:12:58 +00:00
byteswap.hh
sim: Add gtoh/htog helpers that take an explicit endianness
2018-02-16 09:25:14 +00:00
clock_domain.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
clock_domain.hh
sim: Fix clock_domain unserialization
2016-04-01 16:22:44 +01:00
ClockDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
clocked_object.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
clocked_object.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
ClockedObject.py
pwr: Enable multiple power models per component
2017-11-16 16:15:12 +00:00
core.cc
base, sim, dev: Remove SWIG
2017-05-02 12:37:32 +00:00
core.hh
sim: simulate with multiple threads and event queues
2013-11-25 11:21:00 -06:00
cxx_config_ini.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
cxx_config_ini.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
cxx_config.cc
config: Add the ability to read a config file using C++ and Python
2014-10-16 05:49:37 -04:00
cxx_config.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
cxx_manager.cc
misc: Fix order of object construction in the CxxConfigManager
2017-02-09 19:11:23 -05:00
cxx_manager.hh
sim: Decouple draining from the SimObject hierarchy
2015-07-07 09:51:05 +01:00
debug.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
debug.hh
sim: Add relative break scheduling
2015-10-09 14:27:09 -05:00
drain.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
drain.hh
base, sim, dev: Remove SWIG
2017-05-02 12:37:32 +00:00
dvfs_handler.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
dvfs_handler.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
DVFSHandler.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
emul_driver.hh
syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead
2016-11-09 14:27:40 -06:00
eventq_impl.hh
sim: Add hooks to implement event reference counting
2017-05-24 14:28:45 +00:00
eventq.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
eventq.hh
misc: Updates for gcc7.2 for x86
2017-12-14 00:27:59 +00:00
faults.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
faults.hh
syscall_emul: [patch 13/22] add system call retry capability
2015-07-20 09:15:21 -05:00
fd_array.cc
misc: Updates for gcc7.2 for x86
2017-12-14 00:27:59 +00:00
fd_array.hh
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
2017-02-27 14:10:15 -05:00
fd_entry.cc
syscall_emul: [patch 10/22] refactor fdentry and add fdarray class
2016-11-09 14:27:42 -06:00
fd_entry.hh
syscall_emul: [patch 10/22] refactor fdentry and add fdarray class
2016-11-09 14:27:42 -06:00
full_system.hh
clang: Fix recently introduced clang compilation errors
2012-03-19 06:35:04 -04:00
futex_map.hh
syscall-emul: Rewrite system call exit code
2017-03-09 22:42:45 +00:00
global_event.cc
sim: Fix resource leak in BaseGlobalEvent
2014-09-09 04:36:32 -04:00
global_event.hh
dev: Distributed Ethernet link for distributed gem5 simulations
2016-01-07 16:33:47 -06:00
init_signals.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
init_signals.hh
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
init.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
init.hh
base, sim, dev: Remove SWIG
2017-05-02 12:37:32 +00:00
initparam_keys.hh
dev: Distributed Ethernet link for distributed gem5 simulations
2016-01-07 16:33:47 -06:00
insttracer.hh
arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.
2017-12-13 23:51:59 +00:00
InstTracer.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
linear_solver.cc
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
linear_solver.hh
sim: Adding thermal model support
2015-05-12 10:26:47 +01:00
main.cc
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
mathexpr.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
mathexpr.hh
sim: Added library include to fix build errors on clang-703.0.31
2016-06-20 15:34:41 +01:00
mem_state.hh
sim: Fix need to save address space info during serialization.
2017-11-21 16:35:54 +00:00
microcode_rom.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
microcode_rom.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
process_impl.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
process.cc
x86, mem: Rewrite the multilevel page table class.
2018-01-23 20:14:48 +00:00
process.hh
arch, mem, sim: Consolidate and rename the SE mode page table classes.
2018-01-19 20:20:57 +00:00
Process.py
python: Use PyBind11 instead of SWIG for Python wrappers
2017-05-02 12:37:32 +00:00
pseudo_inst.cc
sim: Use named constants for pseudo ops
2017-08-01 18:27:06 +00:00
pseudo_inst.hh
dev: Add m5 op to toggle synchronization for dist-gem5.
2016-10-26 22:48:40 -04:00
py_interact.cc
style: Force Python.h to be included before main header
2017-02-07 15:28:33 +00:00
py_interact.hh
config: Add a --without-python option to build process
2014-10-16 05:49:32 -04:00
root.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
root.hh
sim: Stop using loadState in the Root SimObject.
2017-09-21 17:34:59 +00:00
Root.py
sim: Remove redundant buildEnv import
2016-12-19 16:25:37 +00:00
SConscript
scons: Switch from "guards" to "tags" on source files.
2017-11-27 22:08:50 +00:00
se_signal.cc
syscall-emul: Adds SE mode signal feature
2017-03-09 22:42:45 +00:00
se_signal.hh
syscall-emul: Adds SE mode signal feature
2017-03-09 22:42:45 +00:00
serialize.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
serialize.hh
sim: Use the new BitUnion templates in serialize.hh.
2018-01-20 07:30:10 +00:00
sim_events.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
sim_events.hh
sim: Remove declaration of unused CountedDrainEvent
2017-01-03 17:31:39 +00:00
sim_exit.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
sim_object.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
sim_object.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
simulate.cc
misc: Rename misc.(hh|cc) to logging.(hh|cc)
2017-12-04 23:10:55 +00:00
simulate.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
stat_control.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stat_control.hh
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
stat_register.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
stat_register.hh
base, sim, dev: Remove SWIG
2017-05-02 12:37:32 +00:00
stats.hh
stats: make simTicks and simFreq accessible from stats.hh
2010-04-18 13:23:25 -07:00
sub_system.cc
style: [patch 1/22] use /r/3648/ to reorganize includes
2016-11-09 14:27:37 -06:00
sub_system.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
SubSystem.py
arm: DT autogeneration - Device Tree generation methods
2018-01-29 22:21:30 +00:00
syscall_debug_macros.hh
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
2016-11-09 14:27:40 -06:00
syscall_desc.cc
syscall_emul: Argument retrieval bug fix
2017-05-05 22:21:06 +00:00
syscall_desc.hh
sim-se: Add default to SyscallDesc constructor
2017-11-22 01:05:18 +00:00
syscall_emul_buf.hh
syscall_emul: devirtualize BaseBufferArg methods
2014-10-22 15:53:34 -07:00
syscall_emul.cc
style: change NULL to nullptr in syscall files
2017-03-09 22:42:45 +00:00
syscall_emul.hh
sim-se: Fix fallthrough in prlimit
2018-03-15 20:45:34 +00:00
syscall_return.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
system.cc
sim,cpu,mem,arch: Introduced MasterInfo data structure
2018-04-27 16:00:28 +00:00
system.hh
sim,cpu,mem,arch: Introduced MasterInfo data structure
2018-04-27 16:00:28 +00:00
System.py
sim: Implement load_addr_mask auto-calculation
2017-11-17 10:54:24 +00:00
ticked_object.cc
sim, gdb: Refactor some Event subclasses into lambdas
2017-07-12 20:07:05 +00:00
ticked_object.hh
sim, gdb: Refactor some Event subclasses into lambdas
2017-07-12 20:07:05 +00:00
TickedObject.py
cpu: `Minor' in-order CPU model
2014-07-23 16:09:04 -05:00
voltage_domain.cc
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00
voltage_domain.hh
misc: Add explicit overrides and fix other clang >= 3.5 issues
2015-10-12 04:08:01 -04:00
VoltageDomain.py
power: Add basic DVFS support for gem5
2014-06-30 13:56:06 -04:00
vptr.hh
style: [patch 3/22] reduce include dependencies in some headers
2016-11-09 14:27:40 -06:00